Multi-Bit ADC Overcurrent Detection With Lower Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional overcurrent detection systems using 1-bit sigma delta modulator (SDM) ADCs suffer from high latency and accuracy issues due to the time-consuming conversion from high sampling frequency to low sampling frequency, and adding a comparator in parallel introduces errors and increased power consumption.
Innovation Solution
Implementing multi-bit ADCs that directly convert voltage to digital signals without additional hardware, allowing for faster overcurrent detection with improved accuracy and reduced latency by eliminating the need for parallel comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If 1-bit sigma delta modulator ADC is used for overcurrent detection, then the system can operate with simple hardware structure, but the conversion from high sampling frequency to low sampling frequency causes high latency and accuracy issues
Solution Approach 1:
The patent changes the fundamental parameter of the ADC from 1-bit to multi-bit resolution. This parameter change enables direct conversion at the desired sampling frequency without requiring frequency conversion, thereby eliminating the latency issue while maintaining relatively simple hardware structure through the use of flash ADC architecture
2Device complexity
If 1-bit sigma delta modulator ADC is used for overcurrent detection, then the hardware structure remains simple, but the detection accuracy deteriorates due to frequency conversion requirements
Solution Approach 1:
By changing the ADC resolution parameter from 1-bit to multi-bit (e.g., 3-bit, 4-bit, or higher), the system achieves direct digital output at the input sampling frequency. This eliminates the need for frequency conversion and associated accuracy losses, while the flash ADC architecture keeps the hardware structure relatively simple through parallel comparator design
3Speed
If a comparator is added in parallel to improve detection speed, then the response time improves, but errors increase and power consumption increases
Solution Approach 1:
The patent extracts and eliminates the need for parallel comparators by implementing multi-bit ADC that provides direct digital output. The multi-bit resolution inherently provides the necessary detection speed without requiring additional comparator hardware, thereby removing the source of errors and reduced power consumption while maintaining fast response time
4Loss of time
If multi-bit ADC is implemented for overcurrent detection, then the conversion latency is reduced and detection speed improves, but the device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the multi-bit ADC into multiple independent 1-bit comparators operating in parallel (flash ADC architecture). Each comparator handles one bit of the output, and their results are combined through simple logic circuitry. This segmentation achieves fast conversion latency while keeping individual comparator circuits simple and manageable
5Measurement precision
If multi-bit ADC is implemented for overcurrent detection, then the detection accuracy improves with higher resolution, but the power consumption increases
Solution Approach 1:
The flash ADC architecture segments the multi-bit conversion into parallel 1-bit comparators, each consuming minimal power. The total power consumption scales linearly with the number of bits rather than exponentially, making it more power-efficient than sequential conversion methods while achieving high detection accuracy through multi-bit resolution
Data Source
AI summary
The techniques described herein relate to overcurrent detection with multi-bit analog-to-digital converters (ADCs). An example apparatus includes a multi-bit analog-to-digital converter (ADC) configured to convert an analog signal into a multi-bit digital signal. The example apparatus further includes a threshold detector configured to generate an output signal indicative of an overcurrent condition after a detection of at least a first number of bits of the multi-bit digital signal satisfying a threshold.