Multi-Bit Memory Cell Using Charge Summation for Neural Computing
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Solution Overview
Problem
Existing neural network computing devices face inefficiencies in processing multi-bit operations due to repeated memory access and multiplication operations, which can lead to high power consumption and limited computational speed.
Innovation Solution
A multi-bit cell design that includes a memory for storing weight resistance, a current source for generating weight voltage, and a series of multiplexers and capacitors to perform operations on multi-bit inputs, allowing for efficient generation and summation of charge data, with power-saving features such as turning off the current source when the input is 0.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If repeated memory access and multiplication operations are used for neural network computing, then computational accuracy is maintained, but power consumption increases and computational speed is limited
Solution Approach 1:
The patent replaces traditional digital multiplication and addition operations with analog electrical operations. Resistors represent weights, currents represent inputs, and the system naturally performs weighted summation through parallel electrical connections, eliminating the need for repeated digital computation cycles and reducing power consumption.
Solution Approach 2:
The patent divides multi-bit operations into multiple single-bit processing stages. Each bit position is processed separately through dedicated resistor networks and current mirrors, allowing parallel computation of multiple bits while maintaining precision and enabling efficient summation across different weight magnitudes.
2Productivity
If traditional digital computing methods are used for processing inputs and weights, then operational flexibility is maintained, but processing efficiency is reduced
Solution Approach 1:
The patent creates a universal computing unit that can handle various neural network operations (multiplication, accumulation, activation functions) through a single analog circuit architecture. The same resistor network and current mirror structure processes different weights and inputs by simply changing electrical parameters, maintaining flexibility while improving efficiency.
Solution Approach 2:
The patent changes the operational parameters from digital voltage levels to analog current magnitudes. By varying current strengths and resistor values, the system efficiently processes different weight values and input signals, achieving high processing efficiency while maintaining the adaptability needed for various neural network operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multi-bit cell design significantly reduces power consumption and enhances computational efficiency by performing multi-bit operations through charge data generation and summation, enabling faster processing of neural network operations.
Implementation Method 1
a memory storing a weight resistance corresponding to a multi-bit weight; a current source configured to apply a current to the memory to generate a weight voltage from the weight resistance
Implementation Method 2
a plurality of capacitors connected to the plurality of multiplexers, respectively, each of the capacitors being configured to store a respective weight capacitance, and to generate charge data by performing an operation on the outputted signal and the weight capacitance
Data Source
AI summary
A multi-bit cell includes: a memory storing a weight resistance corresponding to a multi-bit weight; a current source configured to apply a current to the memory to generate a weight voltage from the weight resistance; a plurality of multiplexers connected to each other in parallel and connected to the memory in series, each of the multiplexers being configured to output one signal of the weight voltage and a first fixed voltage based on a multi-bit input; and a plurality of capacitors connected to the plurality of multiplexers, respectively, each of the capacitors being configured to store a respective weight capacitance, and to generate charge data by performing an operation on the outputted signal and the weight capacitance.