Multi-bit Standard Cell Architecture for Mixed Row Design
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Solution Overview
Problem
The mix row cell architecture in IC design presents challenges for design automation tools to achieve balanced density and optimal utilization, leading to low performance and power efficiency due to varying cell heights across rows.
Innovation Solution
The implementation of a multi-bit standard cell architecture with multiple logic cell heights within a bounding box, allowing for different cell architectures to be used in the Automatic Place and Route (APR) process, where taller cells are used for speed-critical paths and shorter cells for low power paths, improving balance and utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If mix row cell architecture with varying cell heights is used, then speed is improved (similar to higher cell height architecture), but area utilization deteriorates (similar to lower cell height architecture)
Solution Approach 1:
The standard cell is segmented into multiple logic cells with different heights (first logic cell with first height, second logic cell with second height). This segmentation allows each logic cell to be optimized for specific functions while maintaining overall cell uniformity, resolving the contradiction between speed and area utilization.
Solution Approach 2:
Different logic cells within the same standard cell have different heights tailored to their specific functional requirements. The first logic cell has a first height optimized for its function, while the second logic cell has a second height optimized for its function, allowing local optimization without affecting overall cell uniformity.
2Area of stationary object
If mix row cell architecture is used, then total area is reduced (similar to lower cell height architecture), but design automation complexity increases
Solution Approach 1:
The standard cell with multiple logic cells of different heights serves multiple functions: it provides both speed optimization and area reduction while maintaining uniform cell height for design automation tools. The bounding box ensures the entire multi-logic-cell structure fits within a standardized cell footprint, making it universally compatible with existing design flows.
3Speed
If mix row cell architecture is used, then speed is maintained (similar to higher cell height architecture), but APR utilization deteriorates
Solution Approach 1:
The invention moves from varying cell heights across different rows to varying logic cell heights within a single standardized cell row. This dimensional reorganization allows APR tools to treat all cells uniformly while still providing the height variations needed for speed optimization, thereby improving APR utilization.
Data Source
AI summary
A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.