Multi-Bit Storage Clock Gating for Lower Toggle Power
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Solution Overview
Problem
Integrated circuits with multiple storage circuits experience high power consumption due to frequent toggling of clock signals at high frequencies, especially when driving a large number of storage circuits like flip flops, leading to significant capacitive loads.
Innovation Solution
A multi-bit storage system that includes a prediction circuit to predict changes in output bits and a clock gating circuit to dynamically generate a trigger signal based on these predictions, reducing unnecessary toggling and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If clock signals are provided at high frequencies to multiple storage circuits, then data update speed is improved, but power consumption increases due to frequent toggling and capacitive loads
Solution Approach 1:
The patent applies dynamics by making the clock signal distribution adaptive rather than static. The prediction circuit dynamically determines whether each storage circuit needs to update its output bit, and the clock gating circuit dynamically enables or disables clock signal transmission based on these predictions. This dynamic approach allows the system to maintain high data update speed when needed while reducing power consumption during periods when updates are not required, directly resolving the contradiction between speed and energy use.
Solution Approach 2:
The patent changes the parameter of clock signal distribution from a fixed high-frequency continuous signal to a variable signal that is enabled only when predicted to be needed. By changing the temporal distribution pattern and frequency of clock signals based on prediction outcomes, the system achieves both fast data updates when required and reduced power consumption when updates are not needed, resolving the speed-power consumption contradiction.
2Reliability
If clock signals are provided continuously to all storage circuits, then reliability of data storage is improved, but power consumption increases due to unnecessary toggling
Solution Approach 1:
The patent implements feedback through the prediction circuit that monitors input bits and predicted output bit changes, then feeds this information back to the clock gating circuit. This feedback mechanism ensures that clock signals are provided only when actually needed for updates, maintaining data storage reliability by ensuring updates occur when necessary while eliminating wasteful energy consumption from unnecessary toggling, thus resolving the contradiction between reliability and energy loss.
Solution Approach 2:
The system performs self-service by using the prediction circuit to autonomously determine when clock signals are needed without external control. The prediction circuit analyzes the input data and automatically generates predictions about output bit changes, enabling the clock gating circuit to selectively distribute clock signals. This self-service approach maintains reliability by ensuring updates happen when needed while reducing energy loss by avoiding unnecessary clock toggling, resolving the contradiction between reliability and energy efficiency.
Data Source
AI summary
Disclosed herein are embodiments related to a power efficient multi-bit storage system. In one configuration, the multi-bit storage system includes a first storage circuit, a second storage circuit, a prediction circuit, and a clock gating circuit. In one aspect, the first storage circuit updates a first output bit according to a first input bit, in response to a trigger signal, and the second storage circuit updates a second output bit according to a second input bit, in response to the trigger signal. In one aspect, the prediction circuit generates a trigger enable signal indicating whether at least one of the first output bit or the second output bit is predicted to change a state. In one aspect, the clock gating circuit generates the trigger signal based on the trigger enable signal.