Multi-bit Mapping Aware Clock Gating for Wide-bus Segmentation
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Solution Overview
Problem
Current IC design tools lack efficient representations for wide-gates and wide-buses, leading to suboptimal performance and quality of results (QoR) due to the inability to explicitly retain information about multi-input logical operations and multi-bit data units throughout the design flow.
Innovation Solution
Introduce new constructs for wide-gates and wide-buses that are explicitly represented and retained throughout the IC design flow, enabling bidirectional links between these constructs and individual gates/wires, allowing for optimized clock gating and improved multi-bit mapping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wide-bus is divided into subsets of bus-wires for clock gating optimization, then clock gating efficiency is improved, but device complexity increases due to segmentation and multiple enable functions
Solution Approach 1:
The wide-bus is divided into multiple subsets of bus-wires, where each subset corresponds to a unit of information (e.g., 32-bit or 64-bit segments). This segmentation enables independent clock gating control for each subset, improving clock gating efficiency by allowing selective clock enablement based on actual data activity in each segment.
Solution Approach 2:
The patent implements both local enable functions (specific to each register or small group of registers) and global enable functions (applicable to entire bus subsets) that work together in a hierarchical manner. This multi-functional approach allows the same clock gating infrastructure to serve both fine-grained and coarse-grained optimization needs, improving efficiency without proportionally increasing complexity.
2Manufacturing precision
If multi-bit register library cells are used for segments, then manufacturing precision is improved through standardized cells, but adaptability decreases due to fixed width constraints
Solution Approach 1:
The bus-wires are divided into segments that match the width of multi-bit register library cells (e.g., 32-bit or 64-bit segments). This segmentation enables the use of standardized multi-bit register cells, improving manufacturing precision and design reliability through proven, tested components with known timing and power characteristics.
Solution Approach 2:
The patent allows the bus to be segmented into different widths based on the available multi-bit register library cell options. By adjusting the segment width parameter to match library cell capabilities, the design achieves optimal use of standardized cells while maintaining adaptability to different bus widths and configurations through flexible segmentation strategies.
Data Source
AI summary
Systems and techniques are described for optimizing an integrated circuit (IC) design. Some embodiments can select a wide-bus in the IC design. Next, the embodiments can divide the wide-bus into one or more subsets of bus-wires, wherein each subset of bus-wires corresponds to a unit of information. The embodiments can then optimize clock gating for each subset of bus-wires.