Multi-bit Combinational Cell Merging for IC Area Reduction
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Solution Overview
Problem
Current circuit design technologies do not effectively combine single-bit combinational cells into multi-bit combinational cells, missing opportunities for area and power consumption reduction, as they primarily focus on sequential cells rather than combinational cells.
Innovation Solution
The method involves identifying and combining single-bit combinational cells based on proximity, shared signals, and graph clustering to form multi-bit combinational cells, which are then optimized for area, power, and timing performance, with the option to add spare cells for flexibility and improved design convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If single-bit combinational cells are combined into multi-bit combinational cells, then area and power consumption are reduced, but design complexity and timing constraints increase
Solution Approach 1:
The patent combines multiple single-bit combinational cells into multi-bit combinational cells by merging their logic functions. This consolidation reduces the total number of cells and interconnections, thereby decreasing area and power consumption while maintaining the required computational functionality through integrated logic operations.
Solution Approach 2:
The multi-bit combinational cells are designed to perform multiple logic functions simultaneously on different bit positions. By creating universal cells that can handle various combinational operations (AND, OR, NAND, NOR, XOR, etc.) across multiple bits, the design achieves functionality consolidation without proportionally increasing complexity.
2Use of energy by stationary object
If single-bit combinational cells are combined into multi-bit combinational cells, then power consumption is reduced, but timing performance may deteriorate
Solution Approach 1:
The patent applies local quality by optimizing the internal structure of multi-bit combinational cells to maintain fast signal propagation paths for critical timing paths while consolidating non-critical functions. Different bit positions can use different logic implementations based on their timing requirements, allowing power reduction in non-critical paths without sacrificing overall timing performance.
3Area of stationary object
If multi-bit combinational cells are used, then fewer cells are needed reducing area, but routing congestion may increase
Solution Approach 1:
The patent segments the multi-bit combinational cell design into modular components that can be independently placed and routed. By dividing the large multi-bit cell into smaller functional blocks or allowing selective decomposition, the routing complexity is managed more effectively while still achieving area reduction through the overall consolidation of multiple single-bit cells into multi-bit structures.
Data Source
AI summary
Embodiments herein describe a techniques for identifying a first combinational cell 210 in a design for an integrated circuit, identifying a plurality of candidate combinational cells 205 to combine with the first combinational cell using a first criterion. The techniques also include combining the first combinational cell with at least one of the plurality of candidate combinational cells to form a multi-bit (MB) combinational cell 100. Upon determining the MB combinational cell satisfies a performance threshold, the first combinational cell and the at least one of the plurality of candidate combinational cells are replaced with the MB combinational cell in the design.