Multi-Bit Memory Comparator Using One Reference Voltage
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Solution Overview
Problem
Existing multi-bit sensing methods for resistive random access memory (ReRAM) require multiple reference voltage sources (VREFS) on-chip, leading to increased chip area and power consumption, which is inefficient and difficult to implement.
Innovation Solution
A comparator device with a first and second comparator circuit and a current source circuitry that adjusts input or reference signals based on the initial comparison result, allowing for multi-bit sensing without additional VREFs, using a single reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple reference voltage sources (VREFS) are used for multi-bit sensing, then sensing accuracy is improved, but chip area and power consumption increase
Solution Approach 1:
The patent changes the parameter of reference voltage by generating multiple VREF values (first VREF, second VREF, third VREF) through sequential voltage division using a single reference voltage source and capacitor network. This allows multi-bit sensing with different reference levels without increasing chip area, as the same physical components are reused at different voltage states.
Solution Approach 2:
A single reference voltage source and capacitor network serve multiple functions by generating different reference voltages (first VREF, second VREF, third VREF) at different time stages. The same hardware components are used universally for all three reference voltage generations, eliminating the need for separate VREF sources for each bit of multi-bit sensing.
2Measurement precision
If multiple reference voltage sources (VREFS) are used for multi-bit sensing, then sensing accuracy is improved, but power consumption increases
Solution Approach 1:
The patent changes the voltage parameter dynamically through capacitive storage and release. The capacitor network stores voltage from the reference source and releases it in controlled stages to generate first VREF, second VREF, and third VREF sequentially, reducing the need for continuous power supply to multiple independent VREF sources.
Solution Approach 2:
The sensing operation is divided into periodic stages with different reference voltages applied at different times. The first comparator uses first VREF at the first time stage, the second comparator uses second VREF at the second time stage, and the third comparator uses third VREF at the third time stage. This periodic, time-multiplexed approach allows accurate multi-bit sensing while keeping power consumption low by activating only one comparator at a time.
3Speed
If multiple comparators are used for parallel multi-bit sensing, then sensing speed is improved, but device complexity increases
Solution Approach 1:
The multi-bit sensing task is segmented into multiple sequential comparison operations. Instead of using multiple comparators simultaneously, the patent divides the sensing into stages with different comparators operating at different time stages, each comparing against a specific reference voltage to determine one bit of the multi-bit data.
Solution Approach 2:
The patent employs periodic action by sequentially activating different comparators at different time stages. The first comparator operates at the first time stage, the second comparator at the second time stage, and the third comparator at the third time stage. This time-multiplexed periodic operation achieves multi-bit sensing with reduced hardware complexity compared to parallel comparator approaches.
Data Source
AI summary
A comparator device for providing an evaluation result derived from comparing an input signal and a reference signal, comprises an interface for receiving the input signal, a reference voltage for providing the reference signal a first comparator circuit configured for a first comparison based on the input signal and the reference signal and to provide a first part of the evaluation result. A second comparator circuit is configured for a second comparison based on the input signal and the same reference signal and to provide a second part of the evaluation result. A current source circuitry is associated with the second comparator circuit and configured for, based on the first part of the evaluation result and for the second comparison, providing an electrical tuning current for scaling the input signal or for scaling the reference signal with the electrical tuning current.