Multi-bit Current Sense Amplifier for STT-MRAM Read Bandwidth
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Solution Overview
Problem
Spin torque transfer magnetoresistive random access memory (STT-MRAM) macros face challenges in achieving short read access time and high read bandwidth while managing high peak current and area overhead, which can degrade power supply voltage integrity and lead to noise-sensitive block failures.
Innovation Solution
A multi-bit current sense amplifier with pipeline current sampling is configured to sense bit line currents using a core sense circuit and bit line precharge branch circuits, generating reference currents to enhance margin, suppress offset, reduce area, and lower peak current and energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of sense amplifiers are used for parallel wide-IO readout, then read access time is shortened and read bandwidth is increased, but peak current increases and area overhead increases
Solution Approach 1:
The patent segments the bit lines into two parts: one part connected to the core sense circuit and another part connected to the bit line precharge branch circuits. This segmentation allows sequential sensing of different bit line groups, enabling wide-IO readout with fewer sense amplifiers, thereby reducing peak current while maintaining high read bandwidth.
Solution Approach 2:
The bit line precharge branch circuits perform preliminary precharging of the bit lines before the core sense circuit performs sensing. This preliminary action prepares the bit lines in advance, allowing the core sense circuit to focus only on the actual sensing operation, thus reducing the number of sense amplifiers needed and lowering peak current requirements.
2Productivity
If a large number of sense amplifiers are used for parallel wide-IO readout, then read access time is shortened, but area overhead increases
Solution Approach 1:
The core sense circuit serves multiple functions: it senses bit line currents from one part of the bit lines and also generates reference currents for comparison. The bit line precharge branch circuits handle precharging for multiple bit lines sequentially. This multi-functionality reduces the total number of sense amplifiers needed, thereby reducing area overhead while maintaining fast read access time.
Solution Approach 2:
By segmenting the bit lines and using sequential sensing with the core sense circuit, the patent reduces the number of parallel sense amplifiers required. The core sense circuit processes different bit line groups in sequence, significantly reducing area overhead compared to having a dedicated sense amplifier for each bit line.
3Productivity
If high peak current is used for fast readout, then read bandwidth is increased, but power supply voltage integrity degrades
Solution Approach 1:
The bit line precharge branch circuits perform preliminary precharging of the bit lines before the core sense circuit performs sensing. This preliminary action reduces the current demand during the actual sensing operation, as the bit lines are already prepared. Consequently, peak current is reduced, preventing power supply voltage droop and maintaining power supply integrity while still achieving high read bandwidth.
Data Source
AI summary
A multi-bit current sense amplifier with pipeline current sampling of a resistive memory is configured to sense a plurality of bit line currents of a plurality of bit lines in a pipeline operation. A core sense circuit is connected to one part of the bit lines and generates a reference parallel resistance current and a reference anti-parallel resistance current. A plurality of bit line precharge branch circuits are connected to the core sense circuit and another part of the bit lines. The bit line currents of the bit lines, the reference parallel resistance current and the reference anti-parallel resistance current are sensed by the core sense circuit and the bit line precharge branch circuits in the pipeline operation so as to sequentially generate a plurality of voltage levels on the core sense circuit in a clock cycle.