Multi-Bit ECC Circuit Using Truncated Parity Matrix Logic
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Solution Overview
Problem
Existing error correction codes (ECCs) for memory systems require significant logic resources to implement multi-bit error correction, which can be inefficient and resource-intensive, especially with emerging memory technologies like MRAM and ReRAM.
Innovation Solution
The use of a systematic check matrix to reduce the logic required for error correction by transforming the generation matrix into a systematic form, truncating rows with higher weights, and forming an error correction circuit based on the truncated parity matrix, thereby minimizing the number of logic gates needed for syndrome generation and error detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction codes are used for multi-bit error correction, then error correction capability is improved, but logic resource consumption increases
Solution Approach 1:
The patent extracts and removes redundant rows from the parity matrix, keeping only the essential rows needed for error correction. This extraction principle directly reduces logic resource consumption while preserving the core error correction capability for multi-bit errors.
Solution Approach 2:
The patent uses a simplified, truncated parity matrix that requires fewer logic gates and less hardware resources compared to traditional full parity matrices. This disposable approach sacrifices some matrix completeness but maintains adequate error correction functionality with reduced resource overhead.
2Measurement precision
If full parity matrix is used for error correction, then correction accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent extracts the essential rows from the full parity matrix that are sufficient for achieving the required correction accuracy. By removing redundant rows, the circuit complexity is reduced while maintaining the ability to detect and correct multi-bit errors effectively.
Solution Approach 2:
The patent applies partial action by using a truncated version of the parity matrix rather than the complete matrix. This partial implementation provides sufficient correction accuracy for the intended application while significantly reducing the circuit complexity and resource requirements.
3Device complexity
If systematic check matrix transformation is applied, then logic reduction is achieved, but transformation complexity increases
Solution Approach 1:
The patent performs the systematic transformation of the generator matrix into systematic form as a preliminary step during the code design phase. This preliminary action prepares the matrix in advance, allowing for subsequent row truncation and simplification without requiring complex transformations during actual error correction operations.
Solution Approach 2:
The patent segments the parity matrix into essential and redundant rows after systematic transformation. This segmentation allows for the removal of unnecessary rows while preserving the structured form needed for efficient error correction, thereby reducing logic gates count while managing transformation complexity.
Data Source
AI summary
A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a G matrix; transforming the G matrix into a systematic form, the transformed G matrix composed of a P matrix and a H matrix; sorting rows of the P matrix according to row weights; determining the number of rows in the P matrix to be truncated in view of a correcting strength and the number of data bits; generating a truncated P matrix by truncating the sorted rows of the P matrix that have a first row weights and keeping the sorted rows of the P matrix that have a second row weights; and forming the error correction circuit according to the truncated P matrix to correct the error of the codeword; wherein the first row weights are greater than the second row weights.