Multi-Bit ECC Circuit Using Truncated Parity Matrix Logic
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Solution Overview
Problem
Existing error correction codes (ECC) for memory systems require significant logic resources to implement multi-bit error correction, which can be inefficient and resource-intensive, especially in emerging memory technologies like MRAM and ReRAM.
Innovation Solution
The use of a systematic check matrix to reduce the logic required for implementing multi-bit error correction codes by truncating rows with higher weights in the parity matrix, minimizing the number of XOR gates needed for syndrome generation and error location determination.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-bit error correction codes are implemented using conventional ECC methods, then error correction capability is improved, but logic resource consumption increases significantly
Solution Approach 1:
The patent extracts and removes redundant rows from the parity check matrix H, specifically eliminating rows that would require excessive XOR gate operations. By selecting only the necessary rows for multi-bit error correction capability, the system achieves the required reliability while significantly reducing the logic resources (XOR gates) needed in the syndrome calculation circuit.
Solution Approach 2:
The patent segments the parity check matrix H into essential and non-essential rows. By dividing the matrix structure and selectively retaining only the critical rows needed for error correction, the system separates the core functionality from redundant components, thereby reducing overall circuit complexity while maintaining error correction capability.
2Measurement precision
If full parity matrix is used for error correction, then correction accuracy is improved, but circuit structure becomes more complex
Solution Approach 1:
The patent extracts the essential functional rows from the complete parity matrix H, removing redundant rows that do not contribute to the core error correction capability. This extraction process maintains the accuracy of error detection and correction by preserving the critical rows needed for syndrome calculation, while eliminating unnecessary circuit complexity.
3Reliability
If more XOR gates are used for syndrome generation, then error correction capability is improved, but resource usage increases
Solution Approach 1:
The patent removes redundant rows from the parity check matrix that would otherwise require additional XOR gates for syndrome generation. By extracting only the essential rows needed for multi-bit error correction, the system maintains full error correction capability while significantly reducing the quantity of logic gates (XOR operations) required in the implementation.
Data Source
AI summary
A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a generation matrix; transforming the generating matrix into a systematic form, wherein the transformed generating matrix is composed of a parity matrix and a check matrix; sorting rows of the parity matrix according to row weights; determining a number of rows in the parity matrix to be truncated; generating a truncated parity matrix by keeping the sorted rows of the P matrix that have weights less than or equal to weights of the truncated rows of the P matrix so as to minimize a number of logic gate operations; and forming an error correction circuit with the number of logic gate operations minimized according to the truncated P matrix to correct the error of the codeword.