Multibit Flip-Flop With Shared Clock Net And Internal Scan Stitching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor technologies face challenges in designing low power multibit flip flops with ultra-low power consumption and compact area requirements, particularly in creating asynchronous reset/set versions and efficiently connecting scan chains within these designs.
Innovation Solution
A multibit flip flop design featuring a cross-couple transmission gate topology with a shared clock net among flip flops, internal scan chain stitching, and reduced transistor count, allowing for asynchronous set/reset functionality without compromising performance, and enabling power optimization and area savings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional multibit flip flop designs are used, then functionality is achieved, but power consumption is high
Solution Approach 1:
The patent merges multiple one-bit flip flops into a single multibit flip flop unit that shares common clock signals, reset signals, and other control resources. This consolidation reduces the total number of transistors and power-consuming elements while maintaining the functionality of multiple bits, directly addressing the contradiction between low power consumption and reliable operation.
Solution Approach 2:
The multibit flip flop design implements universal control signals that can simultaneously manage multiple bits. The shared clock network and control logic provide multi-functional capability, allowing a single structure to handle multiple bits of data with reduced power consumption compared to individual flip flop implementations.
2Area of stationary object
If individual clock buffers are used for each flip flop, then clock signal distribution is reliable, but area and power consumption increase
Solution Approach 1:
The patent combines multiple clock buffer functions into a shared clock distribution network. Instead of placing individual clock buffers for each flip flop, the design uses a common clock tree structure that efficiently distributes clock signals to all bits within the multibit flip flop unit, reducing area while ensuring reliable clock signal delivery.
3Device complexity
If scan chains are connected externally, then testing functionality is achieved, but area and complexity increase
Solution Approach 1:
The patent merges scan chain connections into the internal structure of the multibit flip flop unit. The scan inputs and outputs are integrated within the unit boundaries, creating internal scan paths that reduce external connection complexity while maintaining complete scan chain functionality for testing purposes.
Data Source
AI summary
A multibit flip flop is provided. The multibit flip flop includes: a first stage one-bit flip flop; and a second stage one-bit flip flop, wherein the first stage one-bit flip flop and the second stage one-bit flip flop are configured to share a common clock signal. The first stage one-bit flip flop and the second stage one-bit flip flop are configured to use an inter cell scan input transfer function in a sequential manner. The first stage one-bit flip flop is further configured to provide a scan output signal based on a scan input signal provided at an input port of the first stage one-bit flip flop. The second stage one-bit flip flop is further configured to provide a scan final output signal based on the scan output signal that is provided at an input port of the second stage one-bit flip flop.