Multi-Bit Flip-Flop Circuit With Scan Gates and Lower Transistor Count
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Solution Overview
Problem
Existing multi-bit flip-flops require a significant number of transistors, failing to achieve power and area savings in complex digital systems.
Innovation Solution
A multi-bit flip-flop circuit design with reduced transistor count, utilizing input sub-circuits, primary and secondary latch sub-circuits, and output inverters, along with scan transmission gates instead of multiplexers, to minimize transistor usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If existing multi-bit flip-flop architectures are used, then design area is reduced relative to single-bit flip-flops, but transistor count remains significant leading to failed power and area savings
Solution Approach 1:
The patent merges multiple latch functions into a unified multi-bit flip-flop structure where first and second latch sub-circuits share common control signals and interconnect structures. This consolidation reduces the overall transistor count while maintaining multi-bit storage capability, directly resolving the contradiction between area reduction and transistor quantity.
Solution Approach 2:
The invention implements universal control logic that handles both scan chain testing and normal data storage operations through the same transistor structures. The control signals universally manage multiple latches simultaneously, reducing redundant transistors that would otherwise be needed for separate control paths, thus achieving both area efficiency and low transistor count.
2Area of stationary object
If multi-bit flip-flops are used to store multiple bit signals, then area savings are achieved, but transistor count remains high preventing power savings
Solution Approach 1:
The patent combines multiple latch control functions into shared control structures that reduce total transistor count. By merging the control paths for multiple bits into common logic blocks, the invention reduces both area and the number of active transistors that consume dynamic power during operation.
Solution Approach 2:
The invention changes the operational parameters of the flip-flop by implementing conditional clock gating and tristate control that dynamically adjust power consumption based on operating mode (scan testing vs. normal operation). This parameter adjustment reduces power usage while maintaining the area-efficient multi-bit structure.
3Adaptability or versatility
If scan chain testing is implemented, then testing capability is achieved, but additional transistors increase device complexity
Solution Approach 1:
The patent implements universal control logic that seamlessly handles both scan chain testing and normal data storage operations through the same transistor structures. The control signals universally manage multiple latches whether in test mode or normal operation, adding testing capability without proportionally increasing device complexity.
Solution Approach 2:
The invention introduces dynamic control mechanisms where the same physical structures adapt their function based on control signal states. The latch circuits dynamically switch between scan testing mode and normal storage mode, allowing versatile operation without permanent structural additions that would increase complexity.
Data Source
AI summary
Embodiments disclosed herein relate to device testing using scan chains including various flip-flop devices in a multi-bit flip-flop configuration. A circuit device included herein includes a first flip-flop sub-circuit and a second flip-flop sub-circuit. The first flip-flop sub- circuit is coupled to receive a clock signal and an input, and the second flip-flop circuit is coupled to the first flip-flop sub-circuit. The first flip-flop sub-circuit includes an input sub- circuit, a first latch sub-circuit, a first latch tristate, a second latch sub-circuit, and a first output inverter. The second latch sub-circuit includes a first transmission gate, a first inverter, and a second inverter. The second flip-flop sub-circuit includes a second transmission gate, a first clock tristate, a third latch sub-circuit, a second latch tristate, a fourth latch sub-circuit, and a second output inverter. The fourth latch sub-circuit includes a third transmission gate, a third inverter, and a fourth inverter.