Multibit Flip-Flop Scan Stitching for Low-Power Standard Cells
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Solution Overview
Problem
Current semiconductor technologies face challenges in creating a low power multibit flip flop with ultra-low power consumption and compact area, particularly in designing asynchronous reset/set versions and efficiently connecting scan chains within multibit solutions for synchronous SoC designs.
Innovation Solution
The design incorporates a multibit flip flop with a cross-couple transmission gate topology, sharing a common clock signal among stages, and includes internal scan chain stitching with a true single phase clock design, reducing transistor count and power consumption while maintaining performance, and enabling asynchronous set/reset operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional multibit flip flop designs are used, then functionality is achieved, but power consumption is high
Solution Approach 1:
The patent merges multiple one-bit flip flops into a single multibit flip flop unit that shares common clock signals and control logic. The first and second one-bit flip flops are combined to form a two-bit flip flop that uses a shared clock network and common reset/set logic, reducing overall power consumption while maintaining full functionality. This merging approach eliminates redundant components and reduces the total capacitance that needs to be charged during clock transitions.
2Adaptability or versatility
If more transistors are added to achieve asynchronous reset/set functionality, then functionality is improved, but area increases
Solution Approach 1:
The patent implements universal control logic that handles both synchronous and asynchronous operations using the same hardware structures. The reset and set logic are designed to function in both asynchronous mode (immediate effect) and synchronous mode (clock-edge effect), eliminating the need for separate dedicated circuits for each mode. This multi-functionality approach reduces the total transistor count while providing versatile control capabilities.
3Ease of operation
If scan chains are connected externally, then testing functionality is achieved, but hold buffer insertion increases power consumption
Solution Approach 1:
The patent combines the scan chain functionality directly within the multibit flip flop structure by integrating scan input ports and internal signal routing. The scan signals are propagated through the flip flop stages using existing internal logic paths, eliminating the need for external hold buffers. This integration approach maintains full scan testing capability while reducing the additional power consumption that would be required for external buffer insertion.
4Speed
If separate clock signals are used for each flip flop stage, then timing control is improved, but clock load and power consumption increase
Solution Approach 1:
The patent merges the clock distribution network by providing a single shared clock input that is distributed to all flip flop stages simultaneously. The internal logic of each stage uses this common clock signal to synchronize state transitions. This shared clock approach reduces the total clock capacitance that must be charged and discharged, thereby reducing dynamic power consumption while maintaining proper timing control through the coordinated operation of the shared clock edge across all stages.
Data Source
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Figure 1B
Figure 2A
AI summary
A multibit flip flop is provided. The multibit flip flop (700) includes: a first stage one-bit flip flop (i17); and a second stage one-bit flip flop (i21), wherein the first stage one-bit flip flop and the second stage one-bit flip flop are configured to share a common clock signal (CK). The first stage one-bit flip flop and the second stage one-bit flip flop are configured to use an inter cell scan input transfer function in a sequential manner. The first stage one-bit flip flop is further configured to provide a scan output signal (SCAN_OUT) based on a scan input signal (SI) provided at an input port of the first stage one-bit flip flop. The second stage one-bit flip flop is further configured to provide a scan final output signal based on the scan output signal that is provided at an input port of the second stage one-bit flip flop.