Multi-Bit Flip-Flop Layout With Hold Buffer for Scan Timing

The patent merges the input buffer functionality into a single shared buffer that serves multiple flip-flops. The first input buffer is shared between the first and second flip-flops, and the second input buffer is shared between the third and fourth flip-flops. This consolidation reduces the total number of input buffers from four to two, thereby reducing cell area and power consumption while maintaining the ability to operate flip-flops independently through selective enable signals.

The patent introduces an internal hold buffer as an intermediary component between the first and second scan chains. This hold buffer is specifically configured to maintain signals during scan test operations, preventing time violations that would otherwise occur when shifting data through multiple flip-flops. The hold buffer acts as a mediator that decouples the timing requirements of different scan chains, ensuring reliable scan test operation without significantly increasing overall circuit complexity.

The patent implements a universal scan input structure where the first scan input pin serves as the entry point for scan data that can be distributed to multiple flip-flops through the shared input buffers and internal hold buffer. This multi-functional approach allows a single scan input pin to control scan operations across multiple flip-flops, reducing the total number of scan input pins from what would traditionally be required while maintaining scan test flexibility through the use of enable signals and internal routing.