Multi-Bit Flip-Flop Scan Wiring for Reduced Area Complexity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing multi-bit flip-flop circuits occupy significant area and have complex wiring, making them difficult to design and integrate into electronic circuits effectively.
Innovation Solution
A multi-bit flip-flop circuit design that includes a first and second bit flip-flop, each with input multiplexers, transmission circuits, latches, and signal generation circuits, which reduce area and wiring complexity by using internal wires and external connections to minimize separate wiring for scan inputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional multi-bit flip-flop circuits are used, then data storage and output functions are achieved, but the area occupied is large and wiring complexity is high
Solution Approach 1:
The patent merges the scan input wiring of multiple flip-flops into a single shared wire. The scan input of the first flip-flop, second flip-flop, and subsequent flip-flops are all connected to the same scan input wire, eliminating the need for separate scan input wires for each flip-flop. This merging of wiring resources directly reduces the overall wiring complexity and area occupied by the flip-flop circuit while maintaining full functionality.
Solution Approach 2:
The scan input wire is designed to serve multiple functions: it acts as the data input for the first flip-flop and simultaneously serves as the scan input for all subsequent flip-flops in the chain. This multi-functional design allows a single wire to replace what would traditionally require multiple separate wires, thereby reducing wiring complexity and area without compromising the scan operation capability of each individual flip-flop.
2Reliability
If separate internal wires are provided for scan inputs of each flip-flop, then reliable data input is ensured, but wiring complexity and area increase
Solution Approach 1:
The patent combines multiple scan input connections into a single shared wire that serves all flip-flops. This merging approach maintains reliable data input because the scan chain architecture ensures that data is properly propagated through each flip-flop in sequence, while simultaneously reducing wiring complexity by eliminating redundant separate wires.
Solution Approach 2:
The flip-flops serve themselves in the scan chain configuration where the output of one flip-flop automatically becomes the scan input for the next flip-flop. This self-service mechanism eliminates the need for external separate wiring to provide scan inputs to each flip-flop, as the chain structure inherently provides the necessary connections through the interconnection of flip-flop outputs and inputs.
Data Source
AI summary
A multi-bit flip-flop includes a first bit flip-flop and a second bit flip-flop. The first bit flip-flop includes an input multiplexer that receives a first and second data bits, and outputs one of the first and second data bits as a third data bit; a first transmission circuit; a first latch; a second transmission circuit; and a second latch that outputs a first output data bit. The second bit flip-flop includes an input multiplexer that receives a fourth data bit and the first output data bit, and outputs one of the fourth data bit and the first output data bit as a fifth data bit; a first transmission circuit, a first latch, a second transmission circuit, and a second latch that outputs a second output data bit. The first output data bit is provided from the first bit flip-flop to the second bit flip-flop along an external wire.