Multi-Bit Level Shifter Enable Sharing for Lower Area and Power
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Solution Overview
Problem
Existing dual rail SRAM architectures face increased memory access time and leakage noise due to the voltage difference between high and low voltage domains, and typical single-bit level shifters require excess transistors, consuming more power and area.
Innovation Solution
A multi-bit level shifter design where transistors of the enable function are shared across multiple bits, reducing the number of enable transistors required, and an enable circuit is used to process the enable signal, allowing each level shifter to operate efficiently across different voltage domains.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-bit level shifter is used for each bit, then the voltage level can be shifted correctly between domains, but the number of transistors increases, consuming more power and area
Solution Approach 1:
The patent combines multiple single-bit level shifters into a single multi-bit level shifter unit. The enable circuit shares common transistors (first control transistor connected to VDD, second control transistor connected to ground) across multiple bit positions, while maintaining individual control over each bit through separate enable signals. This merging reduces the total transistor count from O(n) separate level shifters to a shared structure with O(1) control transistors plus individual signal paths.
Solution Approach 2:
The enable circuit transistors serve multiple functions simultaneously - they act as control switches for multiple bit positions, provide voltage domain isolation, and enable selective activation of different bit groups. The first control transistor (connected to VDD) and second control transistor (connected to ground) function as universal control elements that can manage enable signals for multiple level shifter bits within the same voltage domain architecture.
2Ease of operation
If enable transistors are duplicated for each bit, then each bit can be controlled independently, but the area and power consumption increase
Solution Approach 1:
The patent merges the enable control transistors into a shared structure where the first control transistor (connected to VDD) and second control transistor (connected to ground) serve multiple bit positions simultaneously. Each bit position maintains its independent enable signal input, but the physical transistor implementation is shared across the multi-bit unit, reducing area while preserving independent control capability through separate signal paths to the merged transistor gates.
3Loss of energy
If voltage domains are separated for memory logic and array, then power efficiency is improved, but leakage noise and access time increase
Solution Approach 1:
The multi-bit level shifter acts as an intermediary circuit between the low voltage domain (VDD) and high voltage domain (VCC). It receives enable signals from the low voltage domain, processes them through shared control transistors, and outputs level-shifted signals to the high voltage domain memory array. This intermediary structure enables controlled voltage domain transitions, maintaining power efficiency through domain separation while reducing access time through optimized enable signal propagation and shared transistor switching.
Data Source
AI summary
A multi-bit level shifter that has a plurality of level shifters, each of which is configured to receive an input signal in a first voltage domain and provide a corresponding output signal in a second voltage domain. The level shifters each have an enable node. An enable circuit includes an output terminal connected to the enable node of each of the plurality of level shifters, and each of the plurality of level shifters is configured to output the corresponding output signals in response an enable signal received by the enable circuit.