Multi-Bit Level Shifter With Shared Control and N-Well Layout
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Solution Overview
Problem
Integrated circuits (ICs) with multiple power domains face challenges in efficiently managing and converting signals between different voltage levels, leading to increased power consumption and area usage due to the need for multiple level shifters and control circuits.
Innovation Solution
A multi-bit level-shifter (MBLS) circuit that utilizes multiple single-bit level shifters (SBLS) sharing a common control circuit and N-well structures, allowing for power and area savings by toggling between operational states, thereby reducing power consumption and area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple single-bit level shifters each have their own control circuit, then signal conversion between voltage domains is reliable, but power consumption and area usage increase
Solution Approach 1:
The patent combines multiple control circuits into a single shared control circuit that manages multiple single-bit level shifters. This merging approach reduces the total number of control circuits needed, thereby lowering power consumption and area usage while maintaining reliable signal conversion between voltage domains through coordinated control of all level shifters.
Solution Approach 2:
The control circuit is designed with universal functionality to manage multiple level shifters simultaneously. By implementing a multi-functional control circuit that can interface with numerous single-bit level shifters, the system achieves reliable voltage domain conversion across multiple channels without requiring dedicated control circuits for each l shifter, thus optimizing power and area efficiency.
2Reliability
If multiple single-bit level shifters each have their own control circuit, then signal conversion between voltage domains is reliable, but area usage increases
Solution Approach 1:
The patent combines multiple control circuits into a single shared control circuit that manages multiple single-bit level shifters. This merging approach reduces the total number of control circuits needed, thereby lowering power consumption and area usage while maintaining reliable signal conversion between voltage domains through coordinated control of all level shifters.
Solution Approach 2:
The control circuit is designed with universal functionality to manage multiple level shifters simultaneously. By implementing a multi-functional control circuit that can interface with numerous single-bit level shifters, the system achieves reliable voltage domain conversion across multiple channels without requiring dedicated control circuits for each l shifter, thus optimizing power and area efficiency.
3Device complexity
If traditional level shifter approaches are used, then signal conversion is simple, but power consumption and area usage increase with more bits
Solution Approach 1:
The patent segments a multi-bit level shifter into multiple single-bit level shifters that share a common control circuit. This segmentation allows the system to maintain structural simplicity at the individual l shifter level while scaling to handle multiple bits, thereby reducing overall power consumption and area usage compared to traditional approaches where each bit would require a separate control circuit.
Data Source
AI summary
A method includes: forming first, second, and third NWs; forming form first to fourth transistors in corresponding first to fourth groups of active regions, connecting selected transistors amongst the first and second transistors to form first and second input circuits respectively receiving a first input signal in a first domain and a second input signal in the first domain; connecting selected transistors amongst the first and third transistors and amongst the first and fourth transistors to respectively form a first single bit level shifter (SBLS) and a second SBLS; each SBLS operates in the second domain and receives correspondingly versions of the first and second input signals; and connecting selected transistors amongst the first and third transistors to form a control circuit for toggling the first and second SBLSs between a normal and a standby state, a portion of the control circuit and the first SBLS sharing the second NW.


