Multi-Bit Level Shifter With Shared Control and N-Wells
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Solution Overview
Problem
Existing level shifters in integrated circuits (ICs) with multiple power domains face inefficiencies in power consumption and area usage due to the need for multiple control circuits and separate voltage domain N-wells for each single-bit level shifter, leading to increased power and space requirements.
Innovation Solution
A multi-bit level shifter (MBLS) design that incorporates a single control circuit for multiple single-bit level shifters (SBLSs) and shared voltage domain N-wells, allowing for power and area savings by toggling between operational states, reducing power consumption by up to 17% and area usage by up to 39% compared to traditional designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple single-bit level shifters each have separate control circuits and voltage domain N-wells, then signal conversion between voltage domains is achieved, but power consumption and area usage increase
Solution Approach 1:
The patent combines multiple single-bit level shifters into a multi-bit level shifter that shares a common control circuit and common voltage domain N-wells. This merging approach allows the level shifter to handle multiple bits simultaneously while using fewer control circuits and N-well structures, thereby reducing power consumption compared to having separate control circuits for each single-bit level shifter
Solution Approach 2:
The common control circuit serves multiple single-bit level shifters simultaneously, making it a universal control unit that can manage different bits of data. This multi-functional approach eliminates the need for redundant control circuits, reducing overall power consumption while maintaining the ability to convert signals between different voltage domains for multiple data lines
2Reliability
If multiple single-bit level shifters each have separate control circuits and voltage domain N-wells, then signal conversion between voltage domains is achieved, but area usage increases
Solution Approach 1:
The patent merges multiple voltage domain N-well structures into shared common N-wells that serve multiple single-bit level shifters. This consolidation reduces the total number of N-well structures required, thereby decreasing the silicon area occupied by the level shifter circuitry while maintaining the ability to perform voltage domain conversion for multiple data bits
Solution Approach 2:
The common voltage domain N-wells serve as shared infrastructure for multiple single-bit level shifters, allowing them to operate within the same voltage domain boundaries. This universal N-well structure eliminates area redundancy by having each N-well support multiple level shifter units rather than requiring dedicated N-wells for each unit
3Use of energy by moving object
If a multi-bit level shifter uses a single control circuit and shared voltage domain N-wells, then power consumption and area usage are reduced, but device complexity must be managed
Solution Approach 1:
The multi-bit level shifter is segmented into multiple single-bit level shifter units that can be independently configured and controlled through the common control circuit. This segmentation allows the complex function of multi-bit conversion to be broken down into simpler, reusable building blocks, making the overall device easier to design, verify, and maintain despite handling multiple data bits
Data Source
AI summary
A semiconductor device includes: first and second input circuits in a central region and correspondingly configured to operate in a first voltage domain; first and second single bit level shifters (SBLSs) correspondingly in first and second regions at first and second sides of the central region relative to a first direction and electrically coupled correspondingly to the first and second input circuits, and correspondingly configured to operate in a second voltage domain; and a control circuit configured to toggle each of the first and second SBLSs between a normal state and a standby state when a control signal is received from the control circuit.