Multi-Bit Nonvolatile Memory Coding for Capacity and Reliability

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Solution Overview

Problem

Current data storage systems using non-volatile memory, such as NAND flash, face challenges in efficiently storing multiple bits per cell due to error rates and the need for error correction mechanisms, which affect storage capacity and reliability.

Innovation Solution

The implementation of a digital system that uses a combination of Reed Solomon encoding, convolutional codes, and Trellis Coded Modulation (TCM) to store and retrieve data, allowing for multi-bit per cell storage by adjusting code efficiency based on input parameters and utilizing error detection and correction mechanisms to enhance storage capacity and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple bits are stored per memory cell to increase storage capacity, then storage density improves, but error rates increase and reliability deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoiddata reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The data stream is segmented into multiple lanes (first lane, second lane, third lane) that are processed independently through separate encoding paths. Each lane undergoes distinct error correction coding (Reed-Solomon, convolutional, TCM) before being combined for storage. This segmentation allows the system to manage error rates for each individual lane while achieving high overall storage capacity through parallel processing and multiple encoding layers.

Inventive Principle:
Principle #1Segmentation

2Reliability

If error correction mechanisms are implemented to improve reliability, then data integrity improves, but system complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoidencoding system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple error correction mechanisms (Reed-Solomon coding, convolutional coding, Trellis Coded Modulation) are merged into a unified encoding pipeline that processes data through sequential stages. The packed data stream from multiple lanes is combined and subjected to layered error correction, integrating several complex functions into a coordinated system that achieves high reliability without requiring separate independent systems for each encoding type.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If code efficiency is adjusted based on input parameters to optimize storage, then storage capacity adapts, but processing complexity increases

Engineering Contradiction:
Improvestorage adaptabilityVSAvoidprocessing complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The encoding system dynamically adjusts code efficiency and processing parameters based on input data characteristics and storage requirements. The packing arrangement modifies the data stream in real-time to support variable code efficiency levels, allowing the system to adapt between different storage densities and error correction strengths without requiring multiple fixed-configured systems, thereby managing complexity through dynamic reconfiguration rather than static multiplicity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11804856B2Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory
Publication Date: 2023.10.31 MICRON TECHNOLOGY INC
  • US11804856B2 patent drawing
  • US11804856B2 patent drawing
  • US11804856B2 patent drawing

AI summary

A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.