Multi-Bit Nonvolatile Memory Coding for Capacity and Error Control
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Solution Overview
Problem
Current data storage systems using non-volatile memory, such as NAND flash, face challenges in efficiently storing multiple bits per cell due to high error rates and the need for complex error correction mechanisms, which affects storage capacity and reliability.
Innovation Solution
The implementation of a digital system that uses a combination of Reed Solomon encoding, convolutional coding, and Trellis Coded Modulation (TCM) to store and retrieve data, allowing for multi-bit storage by modifying code efficiency based on input parameters and using a packing and mapping arrangement to optimize bit density and error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple bits are stored per memory cell to increase storage capacity, then storage density improves, but error rates increase
Solution Approach 1:
The patent divides the stored bits into different groups with different protection levels. Specifically, it separates bits into a first group and a second group, where the first group uses a first error correction code and the second group uses a second error correction code with different code rates. This segmentation allows the system to handle different error probabilities for different bit positions, thereby managing the increased error rates that come with higher storage density while maintaining overall system reliability.
2Reliability
If complex error correction mechanisms are implemented to reduce errors, then reliability improves, but device complexity increases
Solution Approach 1:
The patent applies different error correction codes to different groups of bits based on their specific error characteristics. The first error correction code is applied to a first group of bits while a second error correction code is applied to a second group of bits. This local quality approach allows the system to optimize error correction for each group's specific needs rather than applying a uniform complex code to all bits, thereby improving reliability while managing overall system complexity.
3Productivity
If code efficiency is increased to improve storage capacity, then productivity improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs dynamic code rate adjustment where different code rates are used for different groups of bits. The system can adaptively select between a first code rate for the first error correction code and a second code rate for the second error correction code based on the specific storage conditions and error characteristics. This dynamic approach allows the system to optimize storage efficiency while maintaining the necessary precision control, as the code rates can be adjusted to match the actual storage conditions rather than requiring fixed high-precision control throughout.
Data Source
AI summary
A digital system, components and method are configured with nonvolatile memory for storing digital data using codewords. The data is stored in the memory using multiple bits per memory cell of the memory. A code efficiency, for purposes of write operations and read operations relating to the memory, can be changed on a codeword to codeword basis based on input parameters. The code efficiency can change based on changing any one of the input parameters including bit density that is stored by the memory. Storing and reading fractional bit densities is described.