Multibit Memory Page Mode Programming Logic
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Solution Overview
Problem
Multilevel-cell (MLC) NAND flash memory devices face longer latency and reliability issues due to the need for finer control over threshold voltages during programming, leading to time-consuming delays and higher bit error rates, especially when programming low pages.
Innovation Solution
The technology involves selecting a program or read operation for an addressed bit in a multilevel cell after another bit has been programmed, allowing for operations that overwrite or preserve the other bit with fewer steps, using logic responsive to the logical status of the other bit, which can change due to memory management algorithms, thereby optimizing programming and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a two-stage programming algorithm is used for MLC low pages, then programming can be performed with existing cell distributions, but programming time increases significantly
Solution Approach 1:
The patent applies dynamics by making the programming algorithm adaptive rather than fixed. The controller dynamically selects between first and second programming algorithms based on real-time status information about the memory cell distribution. This allows the system to optimize programming time by choosing the most efficient algorithm for each specific situation, resolving the contradiction between feasibility and time consumption.
Solution Approach 2:
The patent changes the parameter of algorithm selection based on cell distribution characteristics. By monitoring status information (such as threshold voltage distributions) and adjusting the programming approach accordingly, the system can switch between different programming algorithms to minimize time while maintaining feasibility.
2Manufacturing precision
If finer control over threshold voltages is applied, then programming precision is improved, but programming latency increases
Solution Approach 1:
The patent applies local quality by providing different levels of precision control for different programming scenarios. Instead of always using maximum precision control, the system uses appropriate precision levels locally for each specific cell distribution case, optimizing both precision and time efficiency.
Solution Approach 2:
The system dynamically adjusts the level of threshold voltage control based on the current state of the memory cells. By monitoring status information and adapting the control precision accordingly, the system avoids unnecessary time consumption while maintaining sufficient precision for reliable programming.
3Quantity of substance
If multiple voltage levels are used for programming, then data density is improved, but reliability decreases due to smaller voltage gaps
Solution Approach 1:
The patent implements feedback by using status information about the actual cell distribution to guide programming decisions. This feedback mechanism allows the system to adjust programming parameters in real-time, ensuring that voltage gaps are maintained at levels that ensure reliable data storage while maximizing density.
Solution Approach 2:
The system changes programming parameters based on monitored status information, including voltage distribution characteristics. By adapting parameters such as programming pulse width and amplitude according to actual cell conditions, the system maintains reliable voltage separations even when storing multiple bits per cell.
4Productivity
If status information is monitored and used to select operations, then programming speed is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-establishing status information collection mechanisms and pre-defining programming algorithm selection logic. This allows the system to quickly make programming decisions without complex real-time calculations, improving speed while keeping the added complexity manageable through preparation and optimization.
Data Source
AI summary
A multiple-bit-per-cell, page mode memory comprises a plurality of physical pages, each physical page having N addressable pages p(n). Logic implements a plurality of selectable program operations to program an addressed page. Logic select one of the plurality of selectable program operations to program an addressed page in the particular physical page using a signal that indicates a logical status of another addressable page in the particular physical page. The logical status can indicate whether the other addressable page contains invalid data. The first program operation overwrites the other addressable page, and the second program operation preserves the other addressable page. The first program operation can execute more quickly than the second program operation. The logic can also be applied for programming multiple-bit-per-cell memory not configured in a page mode.