Multi-Bit Delta-Sigma Modulator with Split-Speed Quantization
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Solution Overview
Problem
Current ΔΣ modulators face increased current consumption and circuit scale when improving signal-to-noise ratio (SNR) by increasing sampling frequency or bit number, leading to higher energy consumption and larger circuit sizes.
Innovation Solution
A modulator design that integrates a quantizer operating with a clock cycle shorter than the sampling period, allowing for the generation of a quantized signal with multiple bits while controlling circuit scale and reducing energy consumption by eliminating the need for high-speed operation of components other than the quantizer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the sampling frequency is increased to improve the signal-to-noise ratio, then the SNR is improved, but the current consumption and circuit scale increase
Solution Approach 1:
The patent divides the modulator's operation into two distinct periods: a first period where the integrator performs sampling at a lower frequency, and a second period where the integrator integrates the difference between the input signal and feedback signal. This segmentation allows different parts of the circuit to operate at different speeds, with only the quantizer requiring high-speed operation during the second period, thereby reducing overall current consumption while maintaining SNR performance.
2Measurement precision
If the number of bits of the output signal is increased to improve the signal-to-noise ratio, then the SNR is improved, but the circuit scale and energy consumption increase
Solution Approach 1:
The patent implements dynamic operation modes for the integrator: during the first period, the integrator operates in a low-speed sampling mode with reduced current consumption, and during the second period, it operates in a high-speed integration mode. This dynamic switching allows the circuit to achieve multi-bit quantization performance without requiring all components to operate continuously at high speed, thereby reducing circuit scale and energy consumption while maintaining SNR.
3Measurement precision
If the sampling frequency is increased to improve the signal-to-noise ratio, then the SNR is improved, but the circuit complexity increases
Solution Approach 1:
The patent segments the operational requirements of different circuit components, allowing the integrator to operate at lower speeds during the first period while only the quantizer requires high-speed operation during the second period. This segmentation reduces the overall circuit complexity by eliminating the need for all components to be designed for high-speed operation, thereby maintaining SNR performance with a simpler circuit architecture.
Data Source
AI summary
A modulator that quantizes a first signal into a quantized signal having a plurality of bits includes an integrator performing sampling on the first signal in a first period, and to integrate a difference between the first signal and a reference signal in a second period; and a quantizer receiving a second signal which is an output of the integrator and operating in synchronization with a first clock having a cycle shorter than the first period, the quantizer generating the quantized signal on the basis of the second signal in the first period and outputting the reference signal on the basis of the quantized signal to the integrator.