Multibit Neural Network Circuit Using Capacitive Charge Transfer
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Solution Overview
Problem
Artificial neural networks face challenges with high memory requirements and energy consumption due to the need for analog-to-digital converters when reading from multibit memory arrays, which can negate the benefits of increased memory density.
Innovation Solution
A circuit that samples and scales multibit weights using a capacitance network and buffering circuit, eliminating the need for ADCs by transferring charge through a sampling capacitor and capacitance network, allowing for efficient weighting and scaling of inputs without digital multiply and accumulate operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multibit memory is used to increase memory density, then memory requirements are reduced, but reading from the memory requires ADCs per memory column which consume substantial energy and area
Solution Approach 1:
The patent replaces the electronic ADC conversion system with a capacitive charge transfer system. Instead of converting analog voltages to digital signals using energy-intensive ADCs, the system uses a sampling capacitor to transfer charge directly to a capacitance network, performing the reading operation through purely capacitive mechanisms that consume minimal energy.
Solution Approach 2:
The patent introduces a sampling capacitor as an intermediary component between the multibit memory and the capacitance network. This sampling capacitor mediates the charge transfer process, allowing the memory to interface with the computational circuitry through a simple capacitive coupling rather than requiring complex ADC conversion infrastructure.
2Quantity of substance
If multibit memory is used to increase memory density, then memory requirements are reduced, but ADCs per memory column consume substantial area
Solution Approach 1:
The patent replaces the electronic ADC conversion system with a capacitive charge transfer system. Instead of converting analog voltages to digital signals using energy-intensive ADCs, the system uses a sampling capacitor to transfer charge directly to a capacitance network, performing the reading operation through purely capacitive mechanisms that consume minimal energy.
Solution Approach 2:
The patent extracts and eliminates the ADC component entirely from the system architecture. By removing the need for ADCs per memory column, the design achieves significant area savings while maintaining the ability to read multibit values from memory through the capacitive sampling and scaling mechanism.
3Quantity of substance
If binary ANNs are used to reduce memory requirements, then memory consumption is reduced, but precision is reduced and accuracy goes down
Solution Approach 1:
The patent changes the parameter representation from binary (0 or 1) to multibit analog voltage levels. By allowing memory cells to store multiple bits of information simultaneously through different voltage magnitudes, the system achieves both reduced memory consumption and maintained precision, as the capacitive network can accurately represent and process these multibit values.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the use of multibit memory in artificial neural networks with reduced space and energy requirements, achieving efficient weighting and scaling of inputs while maintaining accuracy without the need for ADCs or digital MAC operations.
Implementation Method 1
a sampling capacitor (112) configured to sample a reading voltage from the memory array as a voltage across the sampling capacitor (112)
Implementation Method 2
a capacitance network (140) connected to the sampling capacitor (112) and configured to scale and weight the voltage across the sampling capacitor (112)
Data Source
Figure 1a
Figure 1b
Figure 2
AI summary
A circuit (100) for an artificial neural network is provided, including a sampling (110) circuit connectable to a multibit memory array (120) in order to sample a reading voltage across a sampling capacitor (112), a capacitance network (140) including a plurality of capacitors (142, 143) and switching elements (144) such that the capacitance network is operable to have a selected capacitance depending on the configuration of the switching elements, and at least one buffering circuit (130) configured to charge the selected capacitance of the capacitance network based on the voltage across the sampling capacitor. The circuit is further configured to operate the capacitance network to at least a first state and a second state, wherein the selected capacitance in at least one of the first and second states depends on an input value (102) to the circuit, to charge the capacitance network in the first state, and to allow charge to redistribute within the capacitance network when it changes from the first to the second state, such that a potential at one or more points (147) within the capacitance network is representative of a scaling of the input value with a weight value represented by the reading voltage. A system including such circuits is also provided.