Multi-Bit Sampler FLL for Fast Lock With Lower Divider Power
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Solution Overview
Problem
Existing frequency synthesizers, particularly those based on phase-locked loops (PLL), face challenges with high power consumption in GHz-level frequency dividers and may fail to settle when the frequency difference between output and reference signals is significant, while frequency locked loops (FLL) offer faster settle times but also consume high power.
Innovation Solution
A frequency locked loop (FLL) design incorporating a multi-bit sampler that sub-samples the output signal with N sampling-clocks of equal frequency and sequential time delays, generating a digital frequency difference to update the sub-sampled parameter, which is then used to generate the output signal, reducing power consumption while maintaining fast settle times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a frequency divider operates at GHz-level frequency to maintain the output signal frequency, then the frequency synthesizer can achieve high output frequency, but the power consumption of the frequency divider increases significantly
Solution Approach 1:
The patent divides the high-frequency sampling task into multiple lower-frequency sampling operations. Instead of using a single GHz-level clock to sample the output signal, the system uses multiple sampling clocks operating at much lower frequencies (e.g., MHz range) that are sequentially offset in time. This segmentation of the sampling function allows the frequency divider to operate at lower frequency while still capturing sufficient signal information through the multi-phase sampling approach.
2Stability of the object's composition
If a phase-locked loop (PLL) is used to achieve frequency lock, then the frequency synthesizer can maintain phase and frequency lock, but the settle time increases and it may fail to settle when frequency difference is large
Solution Approach 1:
The patent introduces a frequency detector as an intermediary component that works in conjunction with the multi-bit sampler. The frequency detector provides frequency error information while the multi-bit sampler captures phase information at multiple time instants. This intermediary frequency detection mechanism enables the system to achieve frequency lock faster than traditional PLLs, reducing settle time while maintaining the ability to achieve and maintain lock even when large frequency differences exist between the output and reference signals.
3Loss of time
If a frequency locked loop (FLL) is used to achieve faster settle time, then the settle time is reduced, but the power consumption increases
Solution Approach 1:
The patent segments the frequency detection and sampling functions into multiple lower-frequency operations. By using multiple sampling clocks at reduced frequencies that are sequentially offset, the system achieves frequency detection capability without requiring a single high-power GHz-level clock. This segmentation approach maintains the fast settle time characteristics of FLL while significantly reducing the power consumption associated with high-frequency operation.
Solution Approach 2:
The system employs periodic multi-phase sampling where N sampling clocks operate at lower frequencies with sequential time offsets. This periodic sampling approach allows the system to reconstruct frequency and phase information over time without requiring continuous high-frequency operation. The periodic nature of the sampling enables accurate frequency measurement while keeping the instantaneous power consumption of the frequency divider much lower than traditional FLL implementations.
Data Source
AI summary
The present disclosure relates to a frequency locked loop including a frequency detection unit, a local oscillator, and a multi-bit sampler. The frequency detection unit is configured to receive a reference frequency parameter and a sub-sampled frequency parameter, and configured to generate a digital frequency difference, which is a difference indication between the reference frequency parameter and the sub-sampled frequency parameter. The local oscillator is configured to generate an output signal based on the digital frequency difference. The multi-bit sampler is configured to update the sub-sampled frequency parameter by sub-sampling the output signal with N (N>=2) sampling-clocks. The N sampling-clocks have a same sampling frequency and are sequentially offset by an equal time delay between adjacent sampling-clocks. The updated sub-sampled frequency parameter monotonically maps an output frequency of the output signal.