Multibit-Cycle SAR ADC Architecture for Faster Low-Power Conversion
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Solution Overview
Problem
SAR ADCs face challenges in processing high-frequency input signals due to their slow conversion speed and increased power dissipation when used in time-interleaved ADCs, leading to buffer drive requirements and noise issues in hierarchical S/H architectures, while pipeline-ADCs introduce nonlinearity and residue amplification challenges.
Innovation Solution
Implement a multibit/cycle SAR ADC architecture with thermometer coding, capacitive interpolation, and additional comparators for balanced loading, along with auto-zero cycles to minimize noise and offset, enabling faster conversion with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If SAR ADC is used for power efficiency, then power consumption is reduced, but conversion speed becomes slow
Solution Approach 1:
The patent divides the conversion process into multiple phases (sampling phase, holding phase, conversion phase) that can overlap in time. The sampling and holding operations are performed in parallel with the conversion process of previous samples, effectively segmenting the critical path and enabling faster conversions without increasing power consumption proportionally.
2Productivity
If time-interleaved ADC with single-stage S/H is used to process high-frequency signals, then sampling rate is increased, but buffer drive requirements and power dissipation increase
Solution Approach 1:
The patent segments the sampling and holding functions into separate stages. The first S/H circuit samples the input signal, and the second S/H circuit holds the sampled value during the conversion process. This segmentation allows each stage to operate at lower power while achieving the required overall sampling rate, reducing the buffer drive requirements compared to a single-stage approach.
3Loss of energy
If hierarchical S/H architecture is used to reduce power, then power dissipation is reduced, but noise and nonlinearity are introduced
Solution Approach 1:
The patent employs a feedback mechanism where the output of the first S/H circuit is fed to the second S/H circuit, and the conversion process uses feedback from the capacitor array to refine the digital output. This feedback approach allows the hierarchical structure to maintain signal integrity while operating at lower power, mitigating the noise and nonlinearity issues that would otherwise result from the multi-stage architecture.
4Speed
If pipeline-ADC is used for faster conversion, then conversion speed is increased, but nonlinearity and residue amplification challenges arise
Solution Approach 1:
The patent replaces the complex multi-stage pipeline architecture with a simplified SAR-based approach that uses capacitive division and binary search. Instead of multiple pipeline stages with residue amplification, the invention uses a single capacitor array that is sequentially adjusted based on comparator feedback, eliminating the nonlinearity and residue amplification challenges inherent in pipeline-ADCs while maintaining fast conversion speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves a power-efficient and reasonably fast single-loop SAR ADC with improved dynamic range and reduced noise, addressing the limitations of traditional SAR and pipeline-ADCs in high-frequency signal processing.
Implementation Method 1
comparing in each step the sampled voltage with a capacitively divided reference voltage provided by the specifically arranged capacitive digital-to-analog converter (C-DAC)
Implementation Method 2
The result of this comparison is then fed back to the C-DAC, which subsequently changes its output for the next comparison step
Data Source
AI summary
A successive approximation register (SAR) analog-to-digital converter (ADC) includes a plurality of differential capacitive digital-to-analog converters (C-DACs), comparators, and an SAR controller. Each differential C-DAC comprises a pair of C-DACs for positive and negative polarities and each C-DAC comprises a capacitor array. A capacitor for each bit position may include a pair of equal-sized capacitors. Each outer comparator is coupled to one of the differential C-DACs and the middle comparator is coupled to a differential output node pair of C-DACs from two differential C-DACs. The SAR controller generates a control signal for the differential C-DACs for each conversion step based on outputs of the comparators. The outputs of the comparators are provided to the differential C-DACs as the control signal without encoding. Single-bit/cycle shorting switches for shorting top plates of capacitors of the C-DACs of same polarity may be closed during a single-bit/cycle conversion.