Multi-Bit SAR ADC Using Sub-DAC Merging for Faster Conversion
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Solution Overview
Problem
Current analog-to-digital converter (ADC) circuits, particularly successive approximation (SA) ADCs, face challenges in achieving high-speed, low power consumption, and small chip real estate while maintaining accuracy, especially at high data rates and GHz signal frequencies.
Innovation Solution
The implementation of multi-bit quantization within the SA ADC loop reduces the number of approximation steps by grouping capacitive elements into sub-DAC circuits for parallel comparisons and using a programmable gain amplifier with a flash ADC circuit to perform coarser and finer quantization at different stages, allowing for error tolerance and redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If successive approximation ADC is used to reduce power consumption and chip area, then power consumption and chip area are reduced, but conversion speed and latency increase
Solution Approach 1:
The patent segments the conversion process into multiple phases where different numbers of bits are converted in parallel at each phase. Instead of converting all bits sequentially as in traditional SA ADC, the capacitor array is divided into sub-arrays that can be activated simultaneously for multi-bit conversion, thereby increasing conversion speed without proportionally increasing power consumption or chip area.
Solution Approach 2:
The patent dynamically adjusts the number of active comparators and capacitor sub-arrays based on the conversion phase. During early phases, more comparators are activated for faster multi-bit conversion; during later phases, fewer comparators are needed as the remaining bits are converted sequentially. This dynamic adjustment optimizes the balance between speed and power consumption throughout the conversion process.
2Speed
If flash ADC circuit is used to achieve high conversion speed with simultaneous comparisons, then conversion speed is improved, but power consumption and device complexity increase
Solution Approach 1:
The patent segments the flash ADC approach by dividing the capacitor array into multiple sub-arrays that can be activated in different phases. Instead of activating all comparators simultaneously as in a full flash ADC, only the necessary sub-arrays are activated at each phase, reducing the number of active comparators and thus lowering power consumption while still achieving multi-bit parallel conversion speedup.
Solution Approach 2:
The patent applies partial action by activating only the necessary number of comparators and capacitor sub-arrays for each conversion phase. Rather than using the full flash ADC architecture with all comparators always active, the system activates exactly the number of comparators needed for the current phase's bit conversion requirements, reducing unnecessary power consumption while maintaining the speed benefits of parallel comparison.
3Productivity
If more comparators are used to process multiple bits per cycle, then conversion speed is improved, but device complexity and chip area increase
Solution Approach 1:
The patent segments the capacitor array into multiple sub-arrays that can be selectively activated. Each sub-array is associated with a subset of comparators, allowing the system to process multiple bits per cycle by activating only the necessary sub-arrays and their associated comparators. This segmentation enables multi-bit parallel conversion without requiring a full set of comparators to be always active, thus reducing device complexity.
Solution Approach 2:
The patent dynamically configures the number of active comparators based on the conversion phase and the number of bits remaining to be converted. During early phases when more bits need conversion, more comparators are activated; during later phases, fewer comparators are needed. This dynamic configuration allows the system to achieve high productivity when needed while reducing device complexity and power consumption when full parallel processing is not required.
Data Source
AI summary
Examples are provided for converting an analog signal to a digital signal by processing more than one bit per cycle in a number of successive approximation cycles. A system may include capacitive sub-DAC circuits and comparators. Switches may isolate the capacitive sub-DAC circuits during one or more first cycles, and merge the sub-DAC circuits during one or more last cycles. A successive approximation register (SAR) may generate digital output signals or DAC digital signals. In another example, a system may include a DAC circuit. An input capacitor may be pre-charged to at least one of an analog input signal and a DAC analog signal. A programmable gain amplifier may amplify an error signal. A multi-bit ADC may convert the amplified error signal to a multi-bit digital signal. An SAR may use the multi-bit digital signal to generate a DAC digital signal or a digital output signal.