Multi-Bit SAR ADC with Narrowing Reference Search Ranges
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Solution Overview
Problem
Conventional SAR ADCs are limited by their single-bit per cycle operation, which hinders high-speed applications and results in increased silicon area, cost, and power consumption, along with comparator mismatch issues in multi-bit per cycle variants.
Innovation Solution
A multi-bit per cycle SAR ADC design featuring a main DAC, a comparing unit, and a reference generator that adjusts reference voltages to reduce search ranges, allowing for simpler switching and reduced comparator offset accuracy, thereby minimizing silicon area, cost, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a conventional SAR ADC converts one bit per cycle, then the circuit complexity is low, but the conversion speed is limited and does not fit for high speed applications
Solution Approach 1:
The patent divides the conversion process into multiple cycles, where each cycle converts multiple bits (e.g., 2 bits per cycle). This segmentation allows the ADC to achieve higher conversion speeds by processing multiple bits in parallel within each cycle, while maintaining a relatively simple circuit architecture by reusing the same DAC and comparator resources across cycles rather than duplicating them
Solution Approach 2:
The patent employs periodic switching of reference voltages and capacitive networks across multiple conversion cycles. The reference generator periodically switches between different reference voltage levels (e.g., ±Vref, ±Vref/2, ±Vref/4) in each cycle, enabling multi-bit conversion per cycle through time-multiplexed operation of the same hardware components
2Speed
If a 2-bit per cycle SAR ADC is proposed to speed up operation, then the conversion speed increases, but triple capacitive ADCs cause triple loading for the previous stage and more comparators are needed causing mismatch issues
Solution Approach 1:
The patent merges multiple capacitive DAC functions into a single shared capacitive network. Instead of using three separate capacitive ADCs as in conventional 2-bit per cycle designs, this invention combines their functionality into one capacitive network that is time-multiplexed across conversion cycles, reducing the loading on the source follower stage from triple to single loading
Solution Approach 2:
The patent makes the DAC and comparator units universal by designing them to handle multiple bits per cycle through periodic reference voltage switching. The same DAC and comparator are reused across different cycles with different reference voltage levels, eliminating the need for multiple dedicated comparators and reducing comparator mismatch issues while achieving 2-bit or multi-bit per cycle conversion
3Speed
If more comparators are used in a multi-bit per cycle SAR ADC, then the conversion speed increases, but comparator mismatch issues need to be resolved increasing design complexity
Solution Approach 1:
The patent uses periodic switching of reference voltages across conversion cycles to enable multi-bit conversion with fewer comparators. By alternating reference voltage levels (e.g., ±Vref in one cycle, ±Vref/2 in the next cycle) and time-multiplexing the comparators, the system achieves high conversion speed without requiring multiple high-precision comparators simultaneously, thus reducing comparator mismatch issues
Solution Approach 2:
The patent changes the reference voltage parameters periodically across conversion cycles rather than using fixed reference levels. The reference generator switches between different voltage magnitudes (Vref, Vref/2, Vref/4) and polarities in different cycles, allowing the same comparator to accurately determine multiple bits through parameter variation rather than requiring multiple comparators with high matching precision
Data Source
AI summary
A main digital-to-analog converter (DAC) receives at least one input and generates an adjusted input. A SAR unit generates a code for controlling the main DAC based on a comparison output of a comparing unit that receives the adjusted input. A reference generator, under control of the generated code, generates at least one reference voltage, which is then forwarded to the comparing unit in each corresponding cycle for defining a search range of each cycle, wherein an absolute value of the reference voltage of a latter cycle is less than the reference voltage of a former cycle such that the search range of the latter cycle is smaller than the search range of the former cycle, and search ranges of all the cycles are centered at a base voltage.