Multi-Bit Flip-Flop Clock Sharing for Low-Power Scan Chains
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Solution Overview
Problem
Conventional master-slave flip-flops consume high power in the clock path, which is not suitable for modern mobile devices with high operating frequencies and limited power sources.
Innovation Solution
A multi-bit flip-flop design that shares a clock signal among multiple flip-flop blocks, using a single inverter to generate an inverted clock signal and employing master and slave latch parts triggered at rising edges, reducing power consumption by minimizing clock path power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional master-slave flip-flop is used, then the flip-flop has high reliability and relatively small size, but it consumes much power in the clock path whenever the clock signal toggles
Solution Approach 1:
The patent merges multiple flip-flop blocks into a multi-bit flip-flop structure that shares a common clock path. By combining N flip-flops into a single integrated structure with shared clocking infrastructure, the total power consumption in the clock path is reduced compared to having separate clock paths for each flip-flop, while maintaining the reliability benefits of the master-slave configuration.
Solution Approach 2:
The patent creates a universal clock path structure that serves multiple flip-flop blocks simultaneously. The shared clock distribution network and common inverter stage provide clock signals to multiple flip-flops through a unified pathway, reducing redundant power consumption that would occur in separate clock paths while maintaining universal functionality across all flip-flop blocks.
2Speed
If the operating frequency is increased for mobile devices, then the processing speed improves, but the power consumption in the clock path increases
Solution Approach 1:
The patent combines multiple flip-flop operations into a synchronized multi-bit structure that processes N bits simultaneously at the same clock frequency. This merging approach allows the system to achieve higher effective throughput at the same operating frequency, or equivalently, to operate at higher frequencies with reduced per-bit power consumption compared to individual flip-flop operations.
Solution Approach 2:
The patent utilizes periodic clock signal action to control the master-slave latch transitions. By synchronizing all flip-flop blocks to transition state at regular periodic intervals defined by the clock signal, the design achieves coordinated high-speed operation while concentrating power consumption into controlled periodic bursts rather than continuous dissipation, improving overall power efficiency at high frequencies.
Data Source
AI summary
A multi-bit flip-flop includes a plurality of multi-bit flip-flop blocks that share a clock signal. Each of the multi-bit flip-flop blocks includes a single inverter and a plurality of flip-flops. The single inverter generates an inverted clock signal by inverting the clock signal. Each of the flip-flops includes a master latch part and a slave latch part and operates the master latch part and the slave latch part based on the clock signal and the inverted clock signal. Here, the flip-flops are triggered at rising edges of the clock signal. Thus, the multi-bit flip-flop operating as a master-slave flip-flop may minimize (or, reduce) power consumption occurring in a clock path through which the clock signal is transmitted.