Multi-Bit Security Registers for Fault-Tolerant SoC Protection
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Solution Overview
Problem
Embedded devices in industrial and automotive applications are vulnerable to fault attacks that compromise their security by manipulating the devices into unintended states, potentially exposing security-critical information or disabling protection mechanisms.
Innovation Solution
A system-on-chip (SoC) with a fault-tolerant security architecture is implemented, featuring security control registers with multi-bit security flags, an eFuse controller for configuration storage, and a device management security controller that manages security settings and applies validation bits to protect against signal corruption during power-on reset, along with hardware firewall modules and initiator side control modules to enforce access privileges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single-bit security flags are used in security control registers, then the device complexity is reduced and ease of manufacture is improved, but the device becomes vulnerable to fault attacks where single-bit manipulation can compromise security
Solution Approach 1:
The security flag is segmented into multiple bits (e.g., 4 bits) instead of using a single bit. Each bit position represents a different security state, and the system requires consistent values across multiple bits to validate security status. This segmentation prevents fault attacks because a single-bit manipulation cannot alter the overall security state without detection.
Solution Approach 2:
The parameter of the security flag is changed from a single-bit representation to a multi-bit representation. This parameter change increases the complexity of fault injection attacks, as attackers would need to manipulate multiple bits simultaneously to compromise security, while the system validates security by checking consistency across all bit positions.
2Reliability
If multi-bit security flags are implemented to protect against fault attacks, then security reliability is improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The multi-bit security flag system is implemented within the existing security control registers of the processor, utilizing the same hardware infrastructure. The security manager component within the device manages the multi-bit flags and performs validation, allowing the system to self-protect against fault attacks without requiring external security hardware or complex manufacturing processes.
Solution Approach 2:
The security control registers, which already exist in the processor for security management, are enhanced to handle multi-bit flags. This universal approach allows the existing register infrastructure to serve both traditional security control functions and the new fault attack protection function, avoiding the need for separate dedicated hardware structures.
3Measurement precision
If validation bits are added to security flags, then detection precision of fault attacks is improved, but the loss of information increases due to additional bits required
Solution Approach 1:
The validation functionality is merged into the security flag structure itself by using multiple bits within the same flag register. Instead of adding separate validation bits in different locations, the system combines the security state representation and validation checking into a single multi-bit flag structure, reducing storage overhead while maintaining detection precision.
Solution Approach 2:
The system uses a small number of additional bits (e.g., 4 bits instead of 1) to provide comprehensive validation. This partial action approach uses just enough additional bits to achieve fault attack detection without excessive overhead, balancing detection precision with storage efficiency by using only the minimum necessary bits for validation.
Data Source
AI summary
A system-on-chip (SoC) is provided that includes security control registers, the security control registers including security flags for security critical assets of the SoC, wherein each security flag includes multiple bits.