Multi-bit Sigma-Delta Modulator DAC with Single Capacitor
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Solution Overview
Problem
Existing sigma-delta modulators face challenges in achieving high signal-to-noise ratio (SNR) due to stability issues and capacitor mismatching, particularly in low-voltage, high-speed applications, where increasing the order or oversampling ratio is not feasible, and high-resolution, high-speed modulators are affected by DAC linear characteristics.
Innovation Solution
A multi-bit sigma-delta modulator with a digital-to-analog converter (DAC) using a switched capacitor structure operating in two phases, where switches connect reference voltages of different polarities across the DAC capacitor, allowing efficient five-level operation without capacitor mismatching, sharing an operational amplifier with the integrator to simplify the circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of ADC bits is increased to achieve high resolution, then the signal-to-noise ratio is improved, but the DAC linear characteristics are degraded due to capacitor mismatching
Solution Approach 1:
The multi-bit DAC is segmented into multiple single-bit DACs, each handling a specific bit position. This segmentation isolates the capacitor mismatching effects to individual bit positions rather than affecting the entire DAC linearity, thereby maintaining high signal-to-noise ratio while mitigating DAC linear characteristic degradation
Solution Approach 2:
The invention discards the problematic multi-bit DAC structure with its capacitor mismatching issues and recovers functionality through multiple single-bit DACs. The single-bit DACs use simpler capacitor structures that are less susceptible to mismatching, and their combined output reconstructs the high-resolution signal without inheriting the original DAC's linearity problems
2Measurement precision
If the order of the modulator is increased to improve signal-to-noise ratio, then the quantization noise is reduced, but the stability is degraded and the available signal range is reduced
Solution Approach 1:
The invention employs dynamic element matching (DEM) techniques where the assignment of capacitors to different DAC output levels is dynamically changed over time. This dynamic redistribution equalizes the impact of capacitor mismatching across multiple cycles, maintaining modulator stability while achieving high signal-to-noise ratio through the multi-bit DAC structure
3Measurement precision
If the oversampling ratio is increased to improve signal-to-noise ratio, then the quantization noise is reduced, but the circuit must operate at high speed which is not suitable for low-voltage applications
Solution Approach 1:
The invention uses multiple single-bit DACs that are essentially simplified copies of a basic single-bit DAC unit. Each copy handles a different bit position, and their combined output achieves high-resolution conversion. This copying approach allows high oversampling ratios to be implemented without requiring proportionally higher operating speeds, as each simple DAC unit can operate efficiently at lower speeds
Data Source
AI summary
A digital-to-analog converter (DAC) for a sigma-delta modulator is provided. The DAC has a switched capacitor structure using an operational amplifier (OP amp) and performs a function exceeding 3-level using a switching method employing only one capacitor in single ended form. Thus, DAC non-linearity caused by capacitor mismatching does not occur, and the number of output levels of the DAC is increased. Also, the DAC capacitor may be applied to a general DAC to increase the ratio of DAC output levels to capacitors.