Multi-Bit SRAM PUF Circuit for Noise-Resistant Authentication
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Solution Overview
Problem
Traditional SRAM PUFs are susceptible to environmental noise, attacks, and have limited entropy and reliability, making them vulnerable to cloning and tampering, which compromises their security and authentication performance.
Innovation Solution
The proposed solution involves modifying SRAM PUFs with additional mechanisms to enhance resilience and security, including balanced charge control on floating nodes and transforming weak PUFs into strong PUFs by using parallel inverters and multiplexers to increase challenge-response space and resistance against adversarial attacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional SRAM PUFs are used to generate unique identifiers, then hardware security is provided with simple approach, but susceptibility to environmental noise and attacks increases
Solution Approach 1:
The SRAM PUF is divided into multiple independent inverter chains, where each chain consists of multiple inverters connected in series. This segmentation allows the system to maintain simplicity while improving reliability through redundancy and diversity in the challenge-response space, making it more resistant to environmental noise and attacks.
Solution Approach 2:
The patent transforms the traditional single-bit PUF response into multi-bit responses by using multiple inverter chains. This dimensional expansion from 1-bit to multi-bit increases the challenge-response space exponentially, providing stronger security against attacks while maintaining the simple SRAM-based implementation.
2Quantity of substance
If SRAM PUFs exploit manufacturing variations to generate PUF responses, then unique identifiers are produced, but entropy and reliability remain limited
Solution Approach 1:
The PUF structure is segmented into multiple inverter chains, each contributing to the overall response. This segmentation increases the total entropy by combining variations from multiple independent chains, thereby improving reliability and consistency of the generated identifiers while maintaining uniqueness.
Solution Approach 2:
The patent creates a composite PUF structure by combining multiple inverter chains with different configurations. This composite approach leverages the manufacturing variations present in each chain to generate higher entropy responses, improving both reliability and uniqueness of the identifiers.
3Device complexity
If traditional SRAM PUF structures are used, then power-up states are determined by manufacturing variations, but vulnerability to modeling and emulation attacks increases
Solution Approach 1:
The patent increases the complexity of the attack space by transitioning from single-bit to multi-bit PUF responses through multiple inverter chains. This dimensional expansion makes modeling and emulation attacks significantly more difficult while maintaining relative structural simplicity in the SRAM implementation.
Solution Approach 2:
The patent introduces dynamic control mechanisms through select signals that can activate or deactivate specific inverter chains based on the challenge input. This dynamic behavior increases the difficulty of modeling and emulation attacks while keeping the physical structure relatively simple and manufacturable.
Data Source
AI summary
An apparatus comprising a pair of inverters configured in a cross-coupled configuration, wherein an inverter of the pair of inverters comprises a static random-access memory (SRAM) physically unclonable function (PUF) circuit, wherein the SRAM PUF circuit comprises an inverter; and an inverter cell comprising a p-channel metal-oxide-semiconductor (PMOS) transistor, an n-channel metal-oxide-semiconductor (NMOS) transistor, and output node, and a control signal input, wherein: (i) the PMOS transistor comprises (a) a drain terminal that is coupled to an output and (b) a source terminal that is coupled to a supply voltage, (ii) the NMOS transistor comprises a gate terminal that is coupled to a gate of the PMOS transistor that inhibits a path between the supply voltage and ground, and (iii) responsive to a low state provided to the control signal input, the control signal input causes the PMOS transistor to charge the output node to the supply voltage.