Multibit Pipelined TDC Quantization to Cut Delay and Power
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Solution Overview
Problem
Conventional time-to-digital converters (TDCs) face limitations in reducing common mode delay and achieving high operating speed due to the need for multiple pipeline stages, which increases power consumption and noise, especially when dealing with time-differential analog input signals.
Innovation Solution
A multi-symbol per stage pipelined TDC system that includes a quantizer and a residue generator, where the quantizer produces multiple digital bits to control the residue generator, reducing the number of pipeline stages and minimizing common mode delay by using default residue control signals and time amplification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple pipeline stages are used in conventional TDCs to achieve high operating speed, then the operating speed improves, but power consumption and noise increase
Solution Approach 1:
The patent combines multiple single-bit quantization operations into a single multibit quantization stage. The quantizer simultaneously produces multiple digital bits (MSBs and LSBs) in one stage, merging the functionality of what would traditionally require multiple sequential pipeline stages. This reduces the total number of stages from multiple to just one or two, thereby reducing power consumption and noise while maintaining high operating speed.
2Speed
If multiple pipeline stages are used in conventional TDCs, then the operating speed improves, but the number of delay elements and device complexity increase
Solution Approach 1:
The patent merges multiple quantization and residue generation operations into a single integrated stage. The quantizer simultaneously generates multiple bits and controls the residue generator to produce the output signal in one unified operation, eliminating the need for multiple sequential pipeline stages and their associated delay elements.
Solution Approach 2:
Within the single stage, the patent segments the quantization process into parallel operations: generating MSBs and LSBs simultaneously, and using these segmented bit components to control different aspects of the residue generation. This segmentation within a unified stage achieves high speed without increasing overall device complexity.
3Measurement precision
If conventional TDCs use multiple pipeline stages with delay elements, then time measurement precision is achieved, but signal-to-noise ratio deteriorates
Solution Approach 1:
The patent combines the quantization and residue generation into a single stage, eliminating multiple delay elements that would introduce noise. The unified approach maintains time measurement precision through simultaneous multibit quantization while avoiding the accumulation of noise from sequential processing stages.
Data Source
AI summary
A multi-symbol per stage pipelined time-to-digital converter (TDC) is presented. The TDC includes a quantizer and a residue generator. The quantizer has an input to accept an analog input first time-differential signal comprising a binary level first edge separated from a binary level second edge by a first duration of time. The first time-differential signal is capable as being represented by m time intervals. The quantizer has an output to supply a first digital code representing Ceil(log2(m)) bit values responsive to (m−1) time interval measurements. The first digital code is a time-to-digital conversion. For example, if the first time-differential signal is capable of being represented as a p-bit binary coded digital word, the quantizer outputs a first digital code representing the Ceil(log2(m)) most significant bit (MSB) values of the p-bit digital word.