Multibit Timestamp Subsystem With Overlapping Bits For On-Chip Debug
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In complex electronic systems, especially those with high integration levels and increasing clock rates, traditional debug and emulation methods face challenges such as diminished visibility and control, leading to longer development cycles and increased costs due to the 'vanishing visibility' issue, where traditional tools like logic analyzers struggle to access system buses and provide adequate debug facilities.
Innovation Solution
A time stamping subsystem that generates a multibit time stamp value, with overlapping least significant and most significant bits transmitted on separate data buses, allowing clients to associate captured data with a precise timestamp, reducing hardware requirements and instrumentation output volume, and enabling efficient debug and emulation capabilities on-chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If traditional debug tools like logic analyzers are used to access system buses, then debug capability is provided, but visibility and control are diminished due to high integration levels and dense packaging
Solution Approach 1:
The time stamp value is segmented into multiple bits that are transmitted sequentially through scan chains. This allows the timestamp information to be distributed across multiple clock cycles and multiple scan chains, enabling precise timing information to be captured even in highly integrated systems where traditional bus access is limited.
Solution Approach 2:
A time stamp generator and distributor acts as an intermediary between the system components and the debug tools. This intermediary captures precise timing information from multiple sources and distributes it through scan chains to various destinations, bridging the gap between the inaccessible internal system state and external debug capabilities.
2Measurement precision
If complete time stamp values are transmitted to all clients, then precise timing information is provided, but hardware requirements and instrumentation output volume increase
Solution Approach 1:
The time stamp value is segmented into multiple bits that are transmitted sequentially through scan chains. This allows the timestamp information to be distributed across multiple clock cycles and multiple scan chains, enabling precise timing information to be captured even in highly integrated systems where traditional bus access is limited.
Solution Approach 2:
Clients receive only the necessary portion of the time stamp value (least significant bits) for their immediate needs, while the most significant bits are transmitted separately through scan chains. This partial transmission approach provides sufficient timing precision for most applications while significantly reducing the hardware footprint and bandwidth requirements compared to transmitting complete timestamp values to all clients simultaneously.
3Area of stationary object
If overlapping bits are used in time stamp transmission, then chip routing area is minimized, but bit alignment and synchronization become more complex
Solution Approach 1:
The system uses dynamic bit shifting and alignment mechanisms where the least significant bits are transmitted first followed by the most significant bits. The comparator and load signal output dynamically adjust the timing and alignment of bit reception across different clients, allowing overlapping bit patterns to be correctly interpreted despite the reduced routing area.
Solution Approach 2:
A load signal output is provided that indicates when the time stamp value should be loaded into the timestamp register. This feedback mechanism ensures proper bit alignment and synchronization by coordinating the reception of overlapping bits across multiple clients with the timestamp register update timing, eliminating alignment errors despite the compact routing arrangement.
4Difficulty of detecting and measuring
If design-for-testability is implemented in the logic design phase, then testability is improved, but design time and cost increase
Solution Approach 1:
The time stamp generator and distributor are integrated into the logic design phase, performing preliminary action to establish testability infrastructure before the main design is completed. By incorporating scan chains and timestamp generation capabilities during the initial design, the system gains comprehensive testability without requiring additional time or resources in later testing phases.
Data Source
AI summary
This invention is time stamping subsystem of an electronic apparatus. A time stamp generator generates a multibit time stamp value including a predetermined number of least significant bits overlapping a predetermined number of most significant bits. Each client receives the least significant bits. Each client associates captured data with a corresponding set of the least significant bits in a message. A central scheduling unit associates most significant bits of the time stamp value with the least significant bits of the message. This associating compares overlap bits of the most significant bits and least significant bits. The most significant bits are decremented until the overlap bits are equal.