Constraint-Aware Multi-Bit Transition Control in Optimization Circuits

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Traditional multiple-bit transition processes for solving combinatorial optimization problems with constraint conditions are complicated, making implementation difficult.

Innovation Solution

A data processing device and method that includes a memory to store state variables and local fields, a transition candidate designation circuit, an update circuit, a cumulative value calculation circuit, a determination circuit, and a control circuit to facilitate multiple-bit transitions while adhering to constraint conditions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a multiple-bit transition process is used to escape local solutions and expand search range, then the search efficiency is improved, but the configuration complexity and implementation difficulty increase

Engineering Contradiction:
Improvesearch efficiencyVSAvoidconfiguration complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the multiple-bit transition process into distinct functional modules: a transition candidate determination unit that identifies which bits should transition, and a transition execution unit that performs the actual state changes. This segmentation allows the complex multiple-bit transition process to be implemented through coordinated simple operations in each module, improving search efficiency while managing configuration complexity through functional decomposition

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent designs the data processing device with universal components that can handle both single-bit and multiple-bit transitions through the same architectural framework. The transition candidate determination unit and execution unit work together to accommodate variable transition sizes (k bits), allowing the system to adapt between different transition strategies without requiring fundamentally different configurations, thus improving efficiency while controlling complexity through multi-functionality

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the number of transitionable bits is increased from one to multiple bits, then the ability to escape local solutions is improved, but the computational overhead increases

Engineering Contradiction:
Improveability to escape local solutionsVSAvoidcomputational overhead
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements a transition candidate determination unit that pre-identifies which k bits should transition before the actual state change occurs. This preliminary determination allows the system to evaluate potential transitions and select optimal candidates without immediately performing all k bit transitions, reducing computational overhead by avoiding unnecessary calculations while maintaining the reliability benefit of multiple-bit transitions for escaping local solutions

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent allows flexible configuration of the transition bit count k, enabling the system to perform partial multiple-bit transitions (transitions of fewer than all possible bits) based on the specific problem requirements. This partial action approach provides a balance between the computational overhead of transitioning all k bits and the reliability benefit of escaping local solutions, allowing optimization based on available computational resources

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP4498293B1Data processing device, data processing program, and data processing method
Publication Date: 2025.12.03 FUJITSU LTD
  • EP4498293B1 patent drawingFigure 1
  • EP4498293B1 patent drawingFigure 2
  • EP4498293B1 patent drawingFigure 3

AI summary

A data processing device including: a memory storing a plurality of values at a first time point, which include: values of state variables at the first time point and included in an evaluation function of a combinatorial optimization problem with a constraint condition; values of first local fields at the first time point and used to specify a change amount of values of the evaluation function by a change in the values of the state variables; and values of second local fields at the first time point and used to specify an amount to be added to the values of the evaluation function when the constraint condition is not satisfied; and a control circuit configured to return the plurality of state variables, the first local fields, and the second local fields to the values at the first time point when the determination circuit has determined not to accept the change.