Multi-branch neural network for IC defect prediction
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Solution Overview
Problem
Conventional defect prediction techniques for integrated circuit (IC) designs are limited by their focus on single layers, failing to account for neighboring layers, which results in incomplete defect detection and reduced accuracy due to high computing resource requirements and simulation latencies.
Innovation Solution
The implementation of multi-branch neural networks that analyze and merge data from multiple IC design layers, including adjacent layers, to predict manufacturing defects by concatenating outputs from separate design layer branches into a merged branch, thereby considering inter-layer effects and improving defect detection accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional single-layer defect prediction techniques are used, then computing resource requirements are reduced, but defect detection accuracy is insufficient due to failure to account for inter-layer effects
Solution Approach 1:
The neural network is divided into multiple independent branches, each responsible for processing a specific IC design layer. This segmentation allows the system to handle complex multi-layer data by breaking it down into manageable separate processing streams that can be executed in parallel, reducing computational overhead while maintaining high defect detection accuracy through specialized layer analysis
Solution Approach 2:
The outputs from multiple separate layer-specific neural network branches are merged into a unified defect prediction result. This merging process integrates information from all layers, enabling the system to detect inter-layer effects and defects that span multiple layers, thereby achieving high detection accuracy without requiring a single overly complex monolithic model
2Reliability
If conventional single-layer defect prediction techniques are used, then simulation latency is reduced, but defect detection completeness is insufficient due to failure to account for neighboring layers
Solution Approach 1:
The simulation process is segmented into parallel branch executions, where each branch independently analyzes a specific layer. This parallel segmentation enables simultaneous processing of multiple layers, reducing total simulation latency while ensuring comprehensive defect detection across all layers and their interactions
Solution Approach 2:
Each neural network branch is designed with universal architecture that can process any IC design layer type. This multi-functionality allows the system to universally handle different layer configurations and interactions, ensuring complete defect detection across diverse multi-layer scenarios without requiring separate specialized models for each layer combination
Data Source
AI summary
A method may include implementing a multi-branch neural network configured to predict manufacturing defects on a layer-of-interest of an integrated circuit (IC) design. The implemented multi-branch neural network may include multiple neural network branches, including a layer-of-interest branch that processes inputs of the layer-of-interest, additional design layer branches that process inputs of the other design layers of the IC design different from the layer-of-interest, and a merged branch. The merged branch may receive, as inputs, outputs of the layer-of-interest branch and the additional design layer branches, and the merged branch may be configured to output a predictor value for the IC design. The method may also include generating, through the multi-branch neural network, a predictor value for a point-of-interest located in the layer-of-interest and predicting a manufacturing defect at the point-of-interest responsive to determination that the predictor value for the point-of-interest meets a defect criterion.