Multi-Bridge Transistor Silicide Stress for Short-Channel Control
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Solution Overview
Problem
Current semiconductor devices face challenges in improving performance and reducing short channel effects in multi-gate transistors, particularly in scaling and current control, due to limitations in gate length and channel design.
Innovation Solution
The semiconductor device incorporates a substrate with alternating regions of p-type and n-type field effect transistors, featuring bridge patterns and epitaxial patterns with silicide patterns that apply different stress properties, enhancing carrier mobility and channel resistance through epitaxial trenches and silicide filling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor scaling is performed to increase integration density, then device density improves, but short channel effects worsen
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional multi-bridge channel structures. Multiple bridge channels are stacked vertically and penetrate the gate structure, creating a 3D configuration that enhances gate control over the channel region while maintaining scaled dimensions, thereby improving density without sacrificing short channel effect suppression
Solution Approach 2:
The channel region is divided into multiple discrete bridge channels that are spaced apart from each other. These segmented channels allow the gate to control current flow through multiple pathways, improving both density and control capability while mitigating short channel effects through the distributed channel architecture
2Reliability
If gate length is increased to improve current control capability, then current control improves, but device scaling is restricted
Solution Approach 1:
The invention moves from single-plane gate control to multi-layer gate structures that wrap around and control multiple bridge channels in three dimensions. This vertical stacking of gates provides enhanced control capability without requiring increased horizontal gate length, enabling continued scaling
Solution Approach 2:
Multiple gate structures are nested around the bridge channels in a layered configuration, with each gate controlling specific channels. This nested arrangement maximizes control capability within compact dimensions, allowing improved current control without proportionally increasing overall device footprint
3Reliability
If bridge patterns are stacked to form multi-bridge channels, then channel control capability improves, but manufacturing complexity increases
Solution Approach 1:
The gate structure serves multiple functions simultaneously: it controls current flow through multiple bridge channels, provides electrical isolation between channels, and acts as a framework for the overall device architecture. This multi-functionality reduces the need for additional separate components, managing complexity while maintaining control capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves channel resistance and contact resistance, leading to enhanced performance and reduced short channel effects, allowing for more efficient scaling and current control in multi-gate transistors.
Implementation Method 1
the first silicide pattern and the second silicide pattern have stress properties different from each other
Data Source
AI summary
A semiconductor device may include a first epitaxial pattern connected to first bridge patterns sequentially stacked on a first region and penetrating through a first gate structure, the first epitaxial layer on a side of the first gate structure and including a first conductivity type impurity, a first silicide pattern on the first epitaxial pattern and overlapping the first bridge patterns in the first direction, a second epitaxial pattern connected to second bridge patterns sequentially stacked on a second region and penetrating through a second gate structure, the second epitaxial layer on a side of the second gate structure and including a second conductivity type impurity different from the first conductivity type impurity, and a second silicide pattern on the second epitaxial pattern and overlapping the second bridge patterns in the third direction, wherein the first silicide pattern and the second silicide pattern have stress properties different from each other.