Multi-Bus Data Partitioning for Single-Threaded Application Communication
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Solution Overview
Problem
Current computing systems face performance bottlenecks due to limited bandwidth in communication channels between host computers and computing subsystems, particularly when using industry standard interfaces like PCI or AGP, which restricts the efficiency of DMA transfers and leads to idle periods or increased overhead.
Innovation Solution
The method involves partitioning state-sequenced information from a single-threaded application and communicating it over multiple I/O buses, allowing separate processing without re-sequencing, thereby leveraging higher bandwidth available in host computer RAM and aggregate I/O interfaces to enhance processing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is grouped into larger amounts for DMA transfer, then the subsystem can process data more efficiently, but the subsystem remains idle for longer periods awaiting data receipt
Solution Approach 1:
The patent segments the data transfer by utilizing multiple I/O buses simultaneously to transport different portions of state-sequenced information in parallel. This allows the subsystem to receive data continuously through multiple channels rather than waiting for a single large DMA transfer, thereby reducing idle time while maintaining processing efficiency.
2Loss of time
If data is broken up into many smaller chunks for DMA transfer, then the subsystem remains less idle, but more overhead is expended in setting up and taking down DMA transfers
Solution Approach 1:
The patent merges multiple I/O buses into a unified data transfer pathway that operates in parallel. By combining the bandwidth capabilities of multiple buses, the system achieves the benefits of smaller data chunks (reduced idle time) without the full overhead cost of managing numerous separate DMA transfers, as the buses are coordinated through a single partitioning mechanism.
3Adaptability or versatility
If industry standard interfaces like PCI or AGP are used for communication, then compatibility is maintained, but bandwidth is limited compared to host computer RAM and aggregate I/O interfaces
Solution Approach 1:
The patent transitions from a single-bus communication pathway to a multi-bus parallel communication architecture. By adding the dimension of multiple simultaneous I/O buses, the system maintains compatibility with standard interfaces while dramatically increasing the aggregate bandwidth available for data transfer, effectively overcoming the bandwidth limitation of individual standard interfaces.
Data Source
AI summary
A system and method communicate information from a single-threaded application over multiple I/O busses to a computing subsystem for processing. In accordance with one embodiment, a method is provided that partitions state-sequenced information for communication to a computer subsystem, communicates the partitioned information to the subsystem over a plurality of input/output busses, and separately processes the information received over each of the plurality of input/output busses, without first se-sequencing the information.