Multi-Carrier CFR Circuit for Low-Complexity Peak Power Reduction
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Solution Overview
Problem
Existing crest factor reduction (CFR) methods for digitally modulated signals in communication systems, such as those used in 4G/4G communication systems, face challenges in achieving optimal power efficiency without high computational complexity and power consumption, especially when dealing with multi-carrier signals, as they often require modifications to data symbols or modulation schemes and result in poor performance for unbalanced signals.
Innovation Solution
A digital CFR processor that uses a constraint-optimization approach with a weighted mean square error (MSE) to minimize crest factor or MSE, incorporating an error generation circuit, linear-phase filter, and summer to reduce the peak-to-average power ratio (PAR) with minimal out-of-band emissions, while maintaining low computational complexity and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional CFR methods (clip-filter, peak cancellation) are used to reduce crest factor, then power efficiency is improved, but computational complexity and circuit power consumption increase significantly
Solution Approach 1:
The signal processing is divided into two independent stages: first applying spread spectrum modulation to the data symbols, then applying CFR processing to the resulting modulated signal. This segmentation allows each stage to be optimized independently, reducing overall computational complexity while maintaining power efficiency benefits.
Solution Approach 2:
The spread spectrum modulation is applied beforehand to the data symbols before CFR processing. This preliminary action transforms the signal into a form where CFR can be more effectively applied, reducing the computational burden of subsequent CFR operations while achieving the desired power efficiency.
2Manufacturing precision
If multiple clip filter stages are cascaded to improve CFR performance, then crest factor reduction is enhanced, but power consumption and chip area increase
Solution Approach 1:
The CFR processing is separated into independent clip-filter stages that operate on the spread spectrum modulated signal. Each stage processes a transformed version of the signal, achieving cumulative CFR performance improvement without requiring excessive cascading of traditional stages, thus controlling power consumption and chip area.
3Manufacturing precision
If GC1115 integrated circuit is used for peak cancellation, then crest factor reduction is achieved, but peak power consumption reaches 1.8 watts
Solution Approach 1:
Spread spectrum modulation is applied to the data symbols before CFR processing, transforming the signal into a form where peak cancellation can be more efficiently performed. This preliminary transformation reduces the computational complexity and power consumption of the subsequent CFR operation, achieving crest factor reduction with lower peak power consumption than conventional methods.
4Manufacturing precision
If polar clipper is used to clip the signal, then crest factor is reduced, but error-vector-magnitude degradation increases for low-power carriers
Solution Approach 1:
The signal is preprocessed with spread spectrum modulation before polar clipping. This preliminary action distributes the signal energy across multiple frequency components, reducing the impact of clipping on any single carrier, particularly low-power carriers. As a result, crest factor reduction is achieved with minimal EVM degradation.
Data Source
AI summary
A crest factor reduction (CFR) circuit reduces the peak-to-average (PAR) power of a digitally modulated signal in a complex baseband is achieved by post-processing the input signal, with negligible increase in out-of-band emissions. The CFR circuit takes advantage of a procedure that solves for an optimum CFR using a constraint-optimization approach. In one embodiment, the CFR circuit, which receives an input signal and provides an output signal, includes: (a) an error generation circuit that receives the input signal and provides an error signal representative of a measure of circuit-induced distortion and a delayed input signal, the delayed input signal being the input signal delayed by a predetermined value; (b) a linear-phase filter receiving the error signal to provide a correction signal; and (c) a summer that subtracts the correction from the delayed input signal to provide the output signal. This circuit can achieve near optimal CFR for arbitrary multi-carrier signals without incurring high computational complexity.