Multi-cell Per Bit Nonvolatile Memory Unit Layout
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Solution Overview
Problem
Existing nonvolatile memory technologies face challenges in data retention due to thin gate oxide layers and increased rewrite cycles, leading to endurance failures and reduced reliability.
Innovation Solution
A single-poly, multi-cell per bit nonvolatile memory unit is designed with serially connected storage cells and a unique layout featuring three oxide define regions separated by trench isolation, utilizing single-poly floating gate transistors with extended floating gates for improved charge storage and reduced memory unit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If gate oxide layer is made thinner to meet device scaling demands, then device scaling is achieved, but data retention deteriorates due to increased electron tunneling from floating gate to substrate
Solution Approach 1:
The patent divides the memory structure into multiple oxide define regions (first, second, and third OD regions) separated by trench isolation regions. This segmentation isolates charge storage in specific regions, preventing charge loss through tunneling while maintaining thin gate oxide layers for scaling compatibility.
Solution Approach 2:
The patent implements different oxide layer configurations in different regions: thin gate oxide layers in active transistor regions for scaling, and thicker oxide layers in trench isolation regions for charge retention. This local differentiation allows simultaneous achievement of device scaling and data retention.
2Length of moving object
If gate oxide layer is made thinner, then device scaling is achieved, but leakage current increases causing charge loss from floating gate
Solution Approach 1:
The patent introduces trench isolation regions as intermediary structures between active memory cells. These isolation regions with thicker oxide layers act as barriers that prevent leakage current from affecting the floating gate, while allowing the main gate oxide layers to remain thin for scaling.
3Productivity
If multiple rewrite cycles are performed, then memory programmability is achieved, but reliability deteriorates as program and erase state differences become too small to recognize
Solution Approach 1:
The patent designs the memory structure with multiple oxide define regions and trench isolations that prevent charge loss before it becomes critical. This preemptive structural design maintains distinguishable program and erase states even after multiple rewrite cycles, cushioning against endurance failures.
4Area of stationary object
If multi-cell per bit structure with serially connected transistors is implemented, then memory unit area is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple memory cells into a single bit unit by serially connecting floating gate transistors between select and word line transistors. This consolidation reduces the overall memory unit area while the systematic layout of oxide define regions manages the complexity through regular patterning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances data retention and reliability by minimizing leakage current and maintaining distinguishable program and erase states, even after multiple rewrite cycles, thereby extending the memory's usable lifespan.
Implementation Method 1
The second floating gate extension is capacitively coupled to a control gate region in the third OD region
Data Source
AI summary
A multi-cell per bit nonvolatile memory (NVM) unit includes a select transistor disposed on a first oxide define (OD) region, a word line transistor disposed on the first OD region, and serially connected floating gate transistors disposed between the select transistor and the word line transistor. A first floating gate extension continuously extends toward a second OD region and adjacent to an erase gate region. A second floating gate extension continuously extends toward a third OD region and is capacitively coupled to a control gate region. A channel length of each of the floating gate transistors is shorter than that of the select transistor or the word line transistor.