Multi-Cell Voltage Detection Circuit With Segmented NMOS Stages
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Solution Overview
Problem
Conventional voltage detection circuits for multi-cell secondary batteries face increased area requirements as the number of cells increases, leading to higher power consumption and larger circuit sizes due to the need for higher withstand voltages in transistors.
Innovation Solution
A voltage detection circuit design that includes a series connection of transistors with specific gate and source connections, reducing the number of elements and area requirements by using enhancement and depletion type NMOS transistors, and a protection circuit to manage voltage fluctuations, allowing for efficient detection of short-circuits and overvoltage conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the number of battery cells increases to obtain higher voltage, then the voltage detection capability is improved, but the area of the voltage detection circuit increases due to higher withstand voltage requirements
Solution Approach 1:
The voltage detection circuit is segmented into multiple stages with different withstand voltage requirements. The first transistor handles the full battery voltage (n cells), while subsequent transistors handle reduced voltages. This segmentation allows each transistor to be sized appropriately for its specific voltage requirement, reducing the total circuit area compared to using full-withstand-voltage transistors throughout.
Solution Approach 2:
Different parts of the circuit are designed with different withstand voltage capabilities matching their local voltage requirements. The first transistor is designed for high voltage (full battery voltage), while later transistors are designed for lower voltages. This local quality optimization ensures that each component is sized appropriately for its specific operating conditions, minimizing overall circuit area.
2Reliability
If the withstand voltage of transistors is increased to handle higher battery voltages, then the voltage detection reliability is improved, but the area of the transistor increases
Solution Approach 1:
The circuit segments the voltage handling responsibilities among multiple transistors. The first transistor (Q1) handles the full battery voltage and is designed with appropriate withstand voltage and channel length for reliability. Subsequent transistors (Q2-Q4) handle reduced voltages and can be designed with shorter channel lengths and smaller areas while maintaining their respective reliability requirements.
Solution Approach 2:
The circuit changes the voltage parameter across different stages. By using a voltage divider configuration and series transistor arrangement, the full battery voltage is divided into smaller voltage drops across different transistors. This parameter change allows later transistors to operate at lower voltages, enabling smaller device areas while maintaining detection reliability through the cascaded architecture.
3Use of energy by stationary object
If the channel length is increased to achieve low power consumption while ensuring withstand voltage, then the power consumption is reduced, but the area of the circuit increases
Solution Approach 1:
The power consumption management is segmented across different transistor stages. The first transistor (Q1) uses a longer channel length to ensure adequate withstand voltage and control leakage current for the full battery voltage. Subsequent transistors (Q2-Q4) can use shorter channel lengths since they handle reduced voltages, thereby reducing their area while maintaining acceptable power consumption through the cascaded voltage reduction approach.
Data Source
AI summary
A voltage detection circuit, a charge control circuit, a charge and discharge control circuit, and a semiconductor device are provided. The voltage detection circuit includes: an input port; a plurality of transistors connected in series and including at least an input transistor including a gate connected to the input port, a source connected to a first power supply terminal, and a drain, and a first transistor including a drain connected to a second power supply terminal, a gate, and a source connected to the gate of the first transistor; and an output port configured to be one of connection points of the plurality of transistors.