Multichannel ADC Fractional Delay Recovery for Channel Synchronization
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Solution Overview
Problem
Multichannel analog-to-digital converter systems face issues such as mismatch between ADCs due to fabrication variations, difficulties in balanced clock distribution, high power consumption, and reduced test yield due to integration of multiple ADCs in the same silicon, which limit their performance in high-speed and high-bandwidth applications.
Innovation Solution
A system utilizing a single ADC with a sample-and-hold circuit that samples and converts multiple analog inputs in a predetermined order, followed by upsampling, digital filtering, and downsampling, along with fractional delay recovery to address synchronization and channel mismatch, thereby reducing channel mismatch, power consumption, and improving test yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple ADCs are used for multichannel conversion, then conversion capability is improved, but fabrication variations cause mismatch between ADCs affecting accuracy
Solution Approach 1:
The patent combines multiple ADC conversion functions into a single ADC by using time-interleaved sampling with multiple sample-and-hold circuits that sequentially sample different channels. This single ADC converts all channels sequentially, eliminating mismatch issues while maintaining multichannel conversion capability through time-multiplexed operation.
Solution Approach 2:
The patent employs periodic sampling where the single ADC sequentially converts multiple channels in a repeating cycle. Each channel is sampled at regular intervals according to a predetermined order, ensuring that all channels are converted with consistent timing characteristics while maintaining high conversion capability through continuous periodic operation.
2Adaptability or versatility
If multiple ADCs are integrated in the same silicon, then multichannel functionality is achieved, but test yield is reduced due to integration
Solution Approach 1:
The patent merges multiple ADC functions into a single ADC device, so only one ADC needs to pass testing rather than multiple ADCs. This single ADC with time-interleaved sampling provides multichannel functionality while improving test yield since the system fails only if the single ADC fails, not if multiple ADCs fail.
3Speed
If multiple ADCs are used for parallel signal processing, then processing speed is improved, but power consumption increases at least n times
Solution Approach 1:
The patent combines multiple ADC conversion operations into a single ADC that operates continuously with time-interleaved sampling. This single ADC processes multiple channels sequentially at high speed, maintaining parallel processing capability while consuming power equivalent to one ADC rather than n times the power of multiple ADCs.
4Measurement precision
If multiple ADCs are used with balanced clock distribution, then synchronous sampling is achieved, but clock skew causes random offsets between channels
Solution Approach 1:
The patent uses a single ADC with a single clock source for all channels, eliminating clock distribution complexity and skew issues. The sample-and-hold circuits for different channels are controlled by the same clock signal, ensuring perfect synchronization without the complexity of balanced clock distribution networks.
Data Source
AI summary
A system including a sample-and-hold circuit for receiving a plurality of analog input signals; an analog-to-digital converter for converting each of the analog inputs to a digital signal; and a processor configured for implementing fractional delay recovery for the analog-to-digital converter. In some embodiments, the fractional delay recovery includes converting each of the plurality of analog input signals to a digital version in the predetermined order; upsampling each digital version in the predetermined order; digitally filtering each upsampled value in the predetermined order; and downsampling each filtered value in the predetermined order.