Multichannel ADC Switching for Delay-Free Synchronized Sampling
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Solution Overview
Problem
Existing multichannel analog-to-digital converters face challenges in increasing conversion throughput and managing conversion delay times, leading to inefficiencies in digital data processing and increased circuit size and power consumption.
Innovation Solution
The proposed analog-to-digital conversion apparatus employs multiple circuit sets with selection circuits and controllers that cyclically switch analog signals at predetermined time differences, allowing for non-overlapping sampling and predictive interpolation to calculate digital data at reference sampling timings, thereby eliminating conversion delay times and optimizing digital data output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple analog-to-digital conversion circuits are used to increase conversion throughput, then productivity is improved, but device complexity increases
Solution Approach 1:
The system divides the multichannel analog signals into multiple groups, with each circuit set handling a specific group. The selection circuit segments the input signals and routes them to appropriate conversion circuits at different time slots, allowing parallel processing of multiple channels while using fewer physical conversion circuits.
Solution Approach 2:
The selection circuit performs cyclic switching among different analog signals at predetermined time differences. Each circuit set converts analog signals periodically at assigned time slots, enabling time-division multiplexing that increases throughput while reusing the same conversion circuits for different channels.
2Productivity
If multiple analog-to-digital conversion circuits are used to increase conversion throughput, then productivity is improved, but power consumption increases
Solution Approach 1:
Instead of using one conversion circuit per channel, the system segments channels into groups and assigns each group to a specific circuit set. This reduces the total number of active conversion circuits, thereby reducing overall power consumption while maintaining multichannel conversion capability through time-division multiplexing.
Solution Approach 2:
Conversion circuits operate periodically at predetermined time slots rather than continuously processing all channels simultaneously. This periodic operation allows circuits to be idle during non-assigned time slots, reducing average power consumption while achieving high throughput through efficient time utilization.
3Device complexity
If cyclic switching is used to process multiple analog signals with fewer circuit sets, then device complexity is reduced, but measurement precision may be affected by timing differences
Solution Approach 1:
The controller pre-calculates conversion delay times for each circuit set based on their respective sampling timings. This preliminary calculation allows the system to compensate for timing differences in subsequent processing, ensuring precise digital data output despite asynchronous sampling across different circuit sets.
Solution Approach 2:
The system measures and calculates the conversion delay time for each circuit set, using this feedback information to adjust and synchronize the digital data output timing. This feedback mechanism ensures that despite different sampling clocks and time slots, all channels are properly synchronized in the final digital output.
Data Source
AI summary
An analog-to-digital conversion apparatus includes a controller. The controller is configured to execute first control processing to cause the selection circuit of each of the circuit sets to perform switching which involves cyclically changing an analog signal to be selected at sampling timings with a predetermined time difference, and second control processing to calculate a digital data item at a reference sampling timing for each of the analog signals based on digital data items obtained from the analog-to-digital converter of the plurality of circuit sets, in accordance with the digital data items with the predetermined time difference, the sampling timings, and the time difference.


