Multi-Channel CRC Circuit Layout for Parallel Error Checking
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Solution Overview
Problem
Conventional CRC circuits are inadequate for multi-channel serial communication systems like HDMI, as they lack the necessary infrastructure to process data in parallel, leading to inefficiencies and increased time delays in error detection.
Innovation Solution
A modified CRC circuit architecture that includes additional modulo-2 adders and flip-flops, allowing for parallel processing of data across multiple channels by generating CRC bits suitable for multi-channel transmission, which reduces the need for storage units and minimizes time delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional CRC circuit is used for multi-channel serial communication, then the circuit structure is simple, but the circuit cannot process data in parallel leading to increased time delays
Solution Approach 1:
The CRC circuit is segmented into multiple independent processing paths, each handling a specific channel. The circuit includes multiple modulo-2 adders and flip-flops arranged in parallel configurations, where each path processes data from a different channel simultaneously. This segmentation enables parallel processing of multi-channel data while maintaining the correctness of CRC calculation for each channel.
2Productivity
If additional modulo-2 adders and flip-flops are added for parallel processing, then data processing efficiency improves, but circuit size increases
Solution Approach 1:
The circuit merges multiple processing paths by sharing common components where possible. The modulo-2 adders and flip-flops are arranged to process multiple channels simultaneously, with the output paths converging to produce the final CRC result. This merging approach allows parallel processing of multiple channels while minimizing the total number of components required compared to having completely separate CRC circuits for each channel.
3Device complexity
If conventional CRC processing is used, then the circuit is easy to implement, but storage units are required increasing circuit complexity
Solution Approach 1:
The circuit performs preliminary actions by pre-positioning the modulo-2 adders and flip-flops in a configuration that allows immediate parallel processing of incoming multi-channel data. The flip-flops are arranged to hold intermediate results from each channel simultaneously, eliminating the need for sequential processing and subsequent storage operations. This preliminary arrangement of processing elements removes the requirement for additional storage units that would otherwise be needed to buffer data between processing stages.
Data Source
AI summary
A method of implementing and manufacturing a cyclic redundancy check circuit for a multi-channel communication system. The method includes creating a generation expression that generates cyclic redundancy check (CRC) bits that satisfies a cyclic redundancy check polynomial of a mono-channel serial communication system with respect to a first point in time, creating a generation expression with respect to points in time that are sequentially delayed as much as the number of multi-channels from the first point in time by applying each point in time to the generation expression, and embodying a circuit corresponding to the generation expression with respect to the most delayed point in time among the created generation expressions. The CRC circuit corresponding to the generation expression will have more modulo-2 adders (e.g., XOR gates) than the number of non-zero coefficients in the selected CRC polynomial.