Multi-Channel CRC Circuit Architecture for Parallel Error Detection
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Solution Overview
Problem
Conventional CRC circuits are inadequate for multi-channel serial communication systems like HDMI, as they lack the necessary infrastructure to process data in parallel, leading to inefficiencies and increased time delays in error detection.
Innovation Solution
A modified CRC circuit architecture that includes additional modulo-2 adders and flip-flops, allowing for parallel processing of data across multiple channels by generating CRC bits suitable for multi-channel transmission, reducing the need for storage units and minimizing time delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional CRC circuits are used in multi-channel serial communication systems, then the circuit structure is simple, but the system cannot process data in parallel leading to increased time delays
Solution Approach 1:
The invention divides the multi-channel data stream into separate channel-specific data streams, with each channel processed by dedicated CRC computation units. This segmentation enables parallel processing of multiple channels simultaneously, directly resolving the contradiction by improving productivity through parallelism while maintaining timely error detection for each channel independently
Solution Approach 2:
The invention transitions from sequential single-channel CRC processing to parallel multi-channel processing by adding spatial dimensionality through multiple processing paths. Each channel operates in its own processing dimension, allowing simultaneous computation without time delays, thus improving productivity while eliminating the time loss associated with sequential processing
2Productivity
If additional modulo-2 adders and flip-flops are added for parallel processing, then parallel processing capability is improved, but circuit complexity increases
Solution Approach 1:
The invention designs universal CRC computation units that can process multiple channels through parallel instantiation. Each unit performs the same CRC function for its assigned channel, and the modular universal design allows easy scaling to different numbers of channels without fundamentally changing the circuit architecture, thus improving productivity while controlling complexity through reuse of standardized blocks
Solution Approach 2:
The invention employs dynamic resource allocation where the number and configuration of parallel CRC units can be adapted to the specific multi-channel requirements. The circuit structure dynamically adjusts to process different numbers of channels efficiently, improving productivity by matching resources to demand while avoiding the complexity of over-provisioning for all possible channel configurations
3Loss of time
If conventional CRC circuits process multi-channel data sequentially, then circuit size is small, but time delays increase in data transmission
Solution Approach 1:
The invention segments the multi-channel data flow into parallel processing paths, with each path handling a specific channel's CRC computation independently. This segmentation eliminates sequential processing bottlenecks, reducing time delays in data transmission while the modular segmented structure achieves efficient space utilization without excessive circuit size increase
4Reliability
If parallel processing infrastructure is implemented, then error detection reliability is improved, but the need for storage units increases
Solution Approach 1:
The invention performs preliminary CRC computation for each channel in parallel as data arrives, rather than storing complete multi-channel data blocks for sequential processing. This preliminary action approach maintains high error detection reliability by computing CRCs immediately for each channel while minimizing storage requirements by processing data in real-time parallel streams rather than requiring bulk storage
Data Source
AI summary
A method of implementing and manufacturing a cyclic redundancy check circuit for a multi-channel communication system. The method includes creating a generation expression that generates cyclic redundancy check (CRC) bits that satisfies a cyclic redundancy check polynomial of a mono-channel serial communication system with respect to a first point in time, creating a generation expression with respect to points in time that are sequentially delayed as much as the number of multi-channels from the first point in time by applying each point in time to the generation expression, and embodying a circuit corresponding to the generation expression with respect to the most delayed point in time among the created generation expressions. The CRC circuit corresponding to the generation expression will have more modulo-2 adders (e.g., XOR gates) than the number of non-zero coefficients in the selected CRC polynomial.