Multichannel Data Receiver Timing Calibration
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Solution Overview
Problem
In computing network systems, the performance of data transmission is compromised by non-idealities such as skew and jitter in signal timing, leading to increased bit error rates and reduced transfer speeds, particularly in multichannel data interfaces where optimal characteristics of commercially available components are not met.
Innovation Solution
A training operation is performed to determine relative timing between clock, data bit, and strobe signals by sampling operations, adjusting delays to align data bit signals with the strobe signal and clock signal, thereby compensating for skew and jitter, using control circuits and delay circuits to set optimal timing relationships.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If commercially available components are used in multichannel data interfaces, then system costs are reduced, but transfer speed and bit error rates are compromised
Solution Approach 1:
The patent performs a training operation before normal data transmission to determine relative timing between clock, data bit, and strobe signals. This preliminary timing calibration compensates for skew and jitter in commercially available components, enabling them to achieve optimal performance without requiring expensive precision components.
2Ease of manufacture
If commercially available components are used in multichannel data interfaces, then system costs are reduced, but bit error rates increase
Solution Approach 1:
The training operation performs preliminary sampling operations to determine timing relationships between signals before actual data transmission. This advance timing calibration reduces bit error rates by compensating for component variations in commercially available interfaces.
Solution Approach 2:
The control circuit uses sampling operations to measure actual timing relationships and adjusts delays accordingly. This feedback mechanism continuously optimizes timing alignment, reducing bit error rates caused by skew and jitter in commercial components.
3Reliability
If timing alignment is performed through sampling operations, then signal timing is aligned reducing bit error rates, but device complexity increases
Solution Approach 1:
The training operation is divided into separate sampling operations: first sampling to determine timing between data bit signals and strobe signal, then second sampling to determine timing between strobe signal and clock signal. This segmentation makes the complex timing calibration process more manageable and implementable.
Solution Approach 2:
The timing calibration is performed once during a preliminary training operation before normal data transmission begins. This one-time preliminary action reduces the need for continuous complex control mechanisms during operation, balancing reliability improvement with acceptable device complexity.
Data Source
AI summary
An apparatus includes a first device having a clock signal and configured to communicate, via a data bus, with a second device configured to assert a data strobe signal and a plurality of data bit signals on the data bus. The first device may include a control circuit configured, during a training phase, to determine relative timing between the clock signal, the plurality of data bit signals, and the data strobe signal. The first device may determine, using a first set of sampling operations, a first timing relationship of the plurality of data bit signals relative to the data strobe signal, and determine, using a second set of sampling operations, a second timing relationship of the plurality of data bit signals and the data strobe signal relative to the clock signal. During an operational phase, the control circuit may be configured to use delays based on the first and second timing relationships to sample data from the second device on the data bus.