Multi-Channel FEC Interleaving for Delay-Free Error Correction
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Solution Overview
Problem
Current data transmission methods in high-speed networks face challenges with bit error correction due to intersymbol interference, leading to reduced signal quality and increased bit error rates, particularly with the increasing bandwidth demands in telecommunications networks.
Innovation Solution
Implementing a data sending and receiving method that utilizes multiple forward error correction (FEC) units with interleaving and de-interleaving processes to distribute bit errors across different FEC units, eliminating the need for the complex and power-consuming interleaving method of writing by row and reading by column, thereby reducing delay and enhancing error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interleaving method of writing by row and reading by column is used to distribute bit errors, then error correction capability is improved, but transmission delay increases and device complexity increases
Solution Approach 1:
The patent divides the data stream into multiple parallel sub-streams, each processed by a separate FEC unit. This segmentation allows error distribution across multiple independent correction units without requiring complex interleaving operations, thereby maintaining error correction capability while reducing transmission delay.
Solution Approach 2:
The patent transitions from a single-dimensional sequential processing approach to a multi-dimensional parallel processing architecture. By distributing data across multiple FEC units operating in parallel, the system achieves error distribution and correction without the time-consuming row-column interleaving operations.
2Reliability
If the interleaving method of writing by row and reading by column is used to distribute bit errors, then error correction capability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the data processing function into multiple parallel FEC units, each handling a subset of data streams. This eliminates the need for complex interleaving and de-interleaving logic, reducing device complexity and power consumption while maintaining the ability to distribute and correct bit errors across the system.
Solution Approach 2:
The patent combines multiple FEC units to work in parallel on different data streams, achieving the error distribution function that would otherwise require complex interleaving. This merging of multiple simpler units replaces a single complex interleaving unit, reducing overall device complexity.
Data Source
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AI summary
An embodiment of the present invention discloses a data sending and receiving method. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed, where the first data stream includes a channel identifier of the first channel; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed, where the second data stream includes a channel identifier of the second channel; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device. The receiving device may perform de-interleaving on the data stream after the interleaving, and send at least data streams obtained through the de-interleaving to different FEC units for decoding, which improves an error correction capability of the receiving device. In addition, in the present invention, an operation of writing by row and reading by column does not need to be performed. Therefore, no delay is generated.