Multichannel Film Semiconductor Package for Low-Impedance Chip Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices are miniaturized and stacked, the increase in channel impedance due to inter-chip connection structures limits the ability to process high-capacity data at high speeds.
Innovation Solution
A semiconductor package that includes a package substrate, a chip stack of semiconductor chips with chip pads, and a multichannel film with conductive lines and an anisotropic conductive film to improve the reliability of electrical connections between the chips and the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor chips are stacked with traditional inter-chip connection structures, then the number of chips can be increased, but channel impedance increases and limits high-speed data processing
Solution Approach 1:
The patent transitions from planar inter-chip connections to three-dimensional vertical connections by wrapping conductive lines around chip side surfaces. This dimensional change allows signals to travel through the thickness of chips rather than across the plane, significantly reducing channel length and impedance while enabling higher chip stacking density.
Solution Approach 2:
The patent embeds conductive lines within an insulating film that wraps around the chip stack, creating a nested structure where the insulating film contains the conductive lines, which in turn connect to chip pads. This nested configuration protects the conductive paths while maintaining compact spacing between stacked chips.
2Productivity
If more chip pads and inter-chip connections are added, then data capacity increases, but channel impedance increases and processing speed decreases
Solution Approach 1:
By routing conductive lines vertically through the chip stack thickness rather than horizontally across chip surfaces, the patent reduces the physical length of signal paths. This dimensional transition maintains high data capacity through multiple parallel channels while minimizing impedance-induced speed limitations.
3Ease of manufacture
If traditional wiring structures are used for inter-chip connections, then manufacturing is simpler, but alignment precision is insufficient and connection reliability is limited
Solution Approach 1:
The patent uses a flexible insulating film that can be wrapped around the chip stack to precisely position conductive lines. This thin film approach provides both mechanical flexibility for manufacturing and precise alignment capability, as the film can be conformally applied to hold conductive elements in exact positions relative to chip pads.
Solution Approach 2:
The insulating film acts as an intermediary between the conductive lines and the chip stack, providing a controlled medium that enables precise alignment. The film serves as both a structural support and a positioning reference, allowing accurate placement of conductive connections without requiring direct mechanical alignment between chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multichannel film reduces inductance by shortening channel lengths and allows for more precise alignment, thereby enhancing the input/output performance for high-speed data processing.
Implementation Method 1
an anisotropic conductive film including an adhesive layer disposed on the first surface of the insulating film to cover the plurality of conductive lines, and conductive particles dispersed in the adhesive layer, the conductive particles being disposed between the plurality of conductive lines and the plurality of chip pads and electrically connecting the plurality of conductive lines and the plurality of chip pads
Implementation Method 2
The insulating film is adhered to the adjacent side surfaces of the plurality of semiconductor chips
Data Source
Figure 1
Figure 2
Figure 3
AI summary
A semiconductor package 100 includes a package substrate 110 having a plurality of substrate pads 115, a chip stack ST including a plurality of semiconductor chips 120 stacked on the package substrate 110, each of the plurality of semiconductor chips 120 having a plurality of chip pads 125, and a multichannel film 150 having a plurality of channels respectively connecting the plurality of chip pads 125 of the plurality of semiconductor chips 120 in a stacking direction Z, the plurality of channels electrically connected to the plurality of substrate pads 115.