Multi-Channel Gate Structure for Semiconductor Leakage Control
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Solution Overview
Problem
Current leakage through channels between adjacent source/drain regions in semiconductor integrated circuits occurs due to the miniaturization and multifunctionalization of electronic devices, necessitating a solution that minimizes current leakage without using insulating dielectric materials to space source/drain regions and substrates apart.
Innovation Solution
A semiconductor integrated circuit device structure is designed with a channel active region comprising multiple channels and gate lines, featuring spacers that penetrate source/drain regions and grooves between channels, along with epitaxial regions of different conductivity types to reduce current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an insulating dielectric material is formed between source/drain region and substrate to space them apart, then current leakage between adjacent source/drain regions is reduced, but device complexity and manufacturing process complexity increase
Solution Approach 1:
The patent removes the insulating dielectric material entirely from the structure. Instead of adding spacing layers between source/drain regions and substrate, the design directly contacts these regions to the substrate, eliminating the harmful insulating layer while maintaining current leakage prevention through alternative means (proper doping and channel design).
Solution Approach 2:
Conventional design adds insulating material to prevent current leakage, but this patent inverts the approach by using properly doped source/drain regions that extend to the substrate surface, allowing direct contact without insulating layers. The prevention of current leakage is achieved through the doping configuration rather than physical separation.
2Reliability
If insulating dielectric material is used to space source/drain region from substrate, then current leakage is minimized, but manufacturing precision requirements increase
Solution Approach 1:
The insulating dielectric material is completely removed from the structure. The source/drain regions are designed to extend directly to and contact the substrate surface, eliminating the need for precise spacing control of insulating layers while maintaining effective current leakage prevention through proper doping configurations.
3Reliability
If channel width is increased to reduce current leakage, then device area increases, but integration density decreases
Solution Approach 1:
The patent applies different doping concentrations and types in different local regions: heavily doped source/drain regions at the substrate interface to prevent current leakage, and appropriately doped channel regions for optimal transistor operation. This localized quality variation allows compact channel dimensions while maintaining leakage prevention.
Solution Approach 2:
The patent changes the electrical parameters (doping concentration and type) of the source/drain regions and channel areas to control current flow characteristics. By adjusting doping levels, the device achieves effective current leakage prevention without requiring increased physical channel width, thus maintaining compact device area.
Data Source
AI summary
A semiconductor integrated circuit device including a substrate with a first element region of a P type and a second element region of an N type, a channel active region that extends in the first element region or the second element region, the channel active region including a plurality of channels, a plurality of gate lines that extend in a second direction intersecting and include a gate metal layer, and a gate insulating film in contact with the gate metal layer, a plurality of first spacers on opposite side portions of respective ones of the gate lines, and a plurality of source/drain regions that are between ones of the plurality of gate lines. The channel active region includes a first channel directly on the substrate, and a second channel spaced apart from the first channel and extends into the gate metal layer.