Multichannel Interpolator with Shared Circuitry for Symbol Rate Conversion
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Solution Overview
Problem
Existing data interpolation methods are limited in efficiently converting digital signals between different sampling frequencies, particularly in multichannel communication systems where a single clock frequency is used, requiring a solution to effectively re-sample signals across multiple channels.
Innovation Solution
A multichannel data interpolator system that generates a select signal and multiple output clocks to interpolate a multichannel output signal frequency, utilizing a network of shift registers and multiplexers with impulse response coefficients to produce a re-sampled output signal, optimizing the process through shared adder and multiplier components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single clock frequency is used in a communication system with programmable symbol rate, then the system can convert data from any symbol rate to that single clock frequency, but the system requires an interpolator to perform frequency conversion which increases device complexity
Solution Approach 1:
The interpolator is divided into multiple stages, where each stage performs a portion of the interpolation operation. The first stage multiplexer and shift register process the input signal, and subsequent stages continue the interpolation sequence, allowing the complex conversion task to be broken into manageable segments that can be executed sequentially
Solution Approach 2:
The system uses periodic sampling and interpolation operations where the interpolator processes the input signal in discrete time intervals. The shift register cycles through stored signal points, and the multiplexer periodically selects and combines these points according to the interpolation ratio, enabling frequency conversion through periodic computational action
2Speed
If data interpolation is performed to change signal sampling frequency, then the signal can be re-sampled at the desired frequency, but the computational complexity increases requiring multiple shift registers and multiplexers
Solution Approach 1:
The shift registers and multiplexers are designed to perform multiple functions: they store signal points, retrieve them in sequence, and combine them according to the interpolation ratio. The same hardware components serve both as memory elements and as active processing elements, reducing the overall number of dedicated components needed
Solution Approach 2:
The system pre-loads signal points into the shift register before the actual interpolation computation begins. This preliminary storage action allows the interpolation algorithm to proceed efficiently by simply reading from the pre-positioned data, rather than accessing the input signal repeatedly during the computation phase
3Ease of manufacture
If linear interpolation is used calculating a desired point between two input signal points, then the computation is simple, but the interpolation precision is limited compared to higher-order methods
Solution Approach 1:
The system changes the interpolation parameter from simple linear combination to a multi-point weighted sum. Instead of using just two points with equal weight, the patent uses N points from the shift register with different weights determined by the impulse response coefficients, improving accuracy while maintaining a systematic computation approach
Data Source
AI summary
Methods, systems, and apparatus can provide a multichannel interpolator while optimizing circuitry reuse.