Multichannel Interpolator Using Time-Multiplexed BRAM
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Solution Overview
Problem
Existing signal generators face limitations in efficiently interpolating multiple data channels with varying data rates, leading to hardware inefficiencies and reduced coefficient output rates due to separate interpolator logic for each channel.
Innovation Solution
A coefficient generator that processes multiple data streams in a multiplexed fashion, using a single interpolator circuit to interpolate multiple data channels with programmable interpolation ratios, and a fractional template filter to suppress image errors, enabling efficient frequency domain conversion and filter coefficient generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate interpolator logic is used for each data channel, then interpolation accuracy is maintained, but hardware complexity and device size increase
Solution Approach 1:
The patent combines multiple separate interpolator circuits into a single shared interpolator that processes multiple data channels sequentially. The interpolator is time-multiplexed across different channels, allowing one interpolator to serve multiple purposes. This merging reduces the total number of interpolator circuits needed while maintaining interpolation accuracy through proper timing and channel management.
Solution Approach 2:
The single interpolator circuit is designed to be universal, capable of processing any data channel by being selectively activated based on the current channel being processed. The interpolator maintains its functional capabilities across all channels it serves, making it a multi-functional component that replaces multiple dedicated interpolators.
2Reliability
If separate interpolator logic is used for each data channel, then channel-specific interpolation is achieved, but the coefficient output rate decreases
Solution Approach 1:
The system implements periodic action by sequentially processing different data channels in a cyclic manner through the single interpolator. Each channel receives interpolated output at regular intervals as the interpolator cycles through the channel sequence. This periodic processing maintains channel-specific interpolation quality while increasing the overall coefficient output rate by keeping the interpolator continuously busy across multiple channels.
Solution Approach 2:
The single interpolator maintains continuous useful action by processing one channel at a time without idle periods. While it switches between channels, it is always performing interpolation work, eliminating the inefficiency of having multiple interpolators where some may be underutilized. This continuous operation maximizes the coefficient generation throughput.
3Device complexity
If a single interpolator circuit is used for multiple data channels, then hardware requirements are reduced, but handling varying data rates becomes more difficult
Solution Approach 1:
The system implements dynamics by making the single interpolator's operation rate and timing adaptable to each data channel's specific requirements. The interpolator can dynamically adjust its processing speed and timing characteristics based on the current channel's data rate. This dynamic behavior allows one static hardware circuit to handle multiple channels with varying rates effectively.
Solution Approach 2:
The system changes operational parameters such as clock timing, processing intervals, and interpolation timing characteristics based on which data channel is currently being processed. By adjusting these parameters dynamically, the single interpolator adapts to different data rates without requiring separate hardware circuits for each rate configuration.
Data Source
AI summary
A multichannel interpolator has an input that receives input data that consists of interleaved channel data from a plurality of data channels. A block random access memory (BRAM) stores data samples from the input data received from the input. Input control logic receives the data samples from the input and places the data samples into the BRAM. Interpolator logic interpolates the data samples to produce output data. The output data is interpolated at an interpolation ratio programmed by a user. The interpolator logic includes a phase generator that calculates a value indicating the interpolation ratio, and a fractional template block that provides a fractional template used to interpolate the data samples to produce the output data, the fraction template block selecting, based on the value calculated by the phase generator. The fractional template is used to interpolate the data samples to produce the output data. Output control logic accesses the BRAM to provide the interpolator logic with the data samples stored in the BRAM as the data samples are needed to interpolate the data samples to produce the output data.